AK4396 Datasheet, PDF (14/38 Pages) Asahi Kasei Microsystems – Advanced Multi-Bit 192kHz 24-Bit ΔΣ DAC

ASAHI KASEI
[AK4396]
SWITCHING CHARACTERISTICS
(Ta=25°C; AVDD=4.75 ∼ 5.25V, DVDD=3.0 ∼ 5.25V)
Parameter
Symbol
min
typ
Master Clock Timing
Frequency
fCLK
7.7
Duty Cycle
dCLK
40
LRCK Frequency
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
Duty Cycle
(Note 18)
fsn
30
fsd
54
fsq
108
Duty
45
PCM Audio Interface Timing
BICK Period
Normal Speed Mode
tBCK
1/128fn
Double Speed Mode
tBCK
1/64fd
Quad Speed Mode
tBCK
1/64fq
BICK Pulse Width Low
tBCKL
30
BICK Pulse Width High
tBCKH
30
BICK “↑” to LRCK Edge
(Note 19) tBLR
20
LRCK Edge to BICK “↑”
(Note 19) tLRB
20
SDATA Hold Time
tSDH
20
SDATA Setup Time
tSDS
20
DSD Audio Interface Timing
DCLK Period
tDCK
1/64fs
DCLK Pulse Width Low
tDCKL
160
DCLK Pulse Width High
tDCKH
160
DCLK Edge to DSDL/R
(Note 20) tDDD
−20
Control Interface Timing
CCLK Period
tCCK
200
CCLK Pulse Width Low
tCCKL
80
Pulse Width High
tCCKH
80
CDTI Setup Time
tCDS
50
CDTI Hold Time
tCDH
50
CSN High Time
tCSW
150
CSN “↓” to CCLK “↑”
tCSS
50
CCLK “↑” to CSN “↑”
tCSH
50
Reset Timing
PDN Pulse Width
(Note 21) tPD
150
max
41.472
60
54
108
216
55
Units
MHz
%
kHz
kHz
kHz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 18. When the normal/double/quad speed modes are switched, AK4396 should be reset by PDN pin or RSTN bit.
Note 19. BICK rising edge must not occur at the same time as LRCK edge.
Note 20. DSD data transmitting device must meet this time.
Note 21. The AK4396 can be reset by bringing PDN pin “L” to “H”. When the states of or DFS1-0 bits change,
the AK4396 should be reset by RSTN bit.
MS0336-E-00
- 14 -
2004/08