AK4396 Datasheet, PDF (30/38 Pages) Asahi Kasei Microsystems – Advanced Multi-Bit 192kHz 24-Bit ΔΣ DAC

ASAHI KASEI
[AK4396]
Addr Register Name
02H Control 3
Default
D7
D6
D5
D4
D3
D2
D1
D0
D/P
DSDM DCKS DCKB
0
DZFB
0
0
0
0
0
0
0
0
0
0
DZFB: Inverting Enable of DZF
0 : DZF pin goes “H” at Zero Detection (Default)
1 : DZF pin goes “L” at Zero Detection
DCKB: Polarity of DCLK (DSD Only)
0 : DSD data is output from DCLK falling edge. (Default)
1 : DSD data is output from DCLK rising edge.
DCKS: Master Clock Frequency Select at DSD mode (DSD only)
0 : 512fs (Default)
1 : 768fs
DSDM: DSD Input Select
0 : Input pin : No.5, 6, 7 (Default)
1 : Input pin : No. 12, 13, 14
When DSDM bit is changed, the AK4396 should be reset by RSTN bit.
D/P: DSD/PCM Mode Select
0 : PCM mode (Default)
1 : DSD mode
When D/P bit is changed, the AK4396 should be reset by RSTN bit.
Addr Register Name
03H Lch ATT
04H Rch ATT
Default
D7
ATT7
ATT7
1
D6
ATT6
ATT6
1
ATT7-0:
Attenuation Level
ATT = 20 log₁₀ (ATT_DATA / 255) [dB]
FFH : 0dB (Default)
00H : Mute
D5
ATT5
ATT5
1
D4
ATT4
ATT4
1
D3
ATT3
ATT3
1
D2
ATT2
ATT2
1
D1
ATT1
ATT1
1
D0
ATT0
ATT0
1
MS0336-E-00
- 30 -
2004/08