AK4396 Datasheet, PDF (32/38 Pages) Asahi Kasei Microsystems – Advanced Multi-Bit 192kHz 24-Bit ΔΣ DAC

ASAHI KASEI
[AK4396]
Master Clock
Reset & Power down
64fs
24bit Audio Data
fs
Mode
setting
Digital Ground
Digital
Supply 3.3V
10u 0.1u
+
1 DVSS
2 DVDD
3 MCLK
4 PDN
5 BICK
6 SDATA
7 LRCK
8 SMUTE
9 DFS0
10 DEM0
11 DEM1
12 DIF0
13 DIF1
14 DIF2
ACKS 28
TST2 27
TST1 26
P/S 25
AK4396 ^{VCOM 24}
AOUTL+ 23
AOUTL- 22
AOUTR+ 21
AOUTR- 20
AVSS 19
0.1u
AVDD 18
VREFH 17
0.1u
VREFL 16
TTL 15
0.1u
1+0u
Lch
LPF
Rch
LPF
Lch Out
Rch Out
+ ^10u
+
10u
Analog
Supply 5V
Analog Ground
Notes:
- BICK = 64fs, LRCK = fs.
- Power lines of AVDD and DVDD should be distributed separately from the point with low impedance of regulator
etc.
- AVSS and DVSS must be connected to the same analog ground plane.
- When AOUT drives some capacitive load, some resistor should be added in series between AOUT and
capacitive load.
- All input pins except pull-down/pull-up pins should not be left floating.
Figure 13. Typical Connection Diagram (AVDD = 5V, DVDD = 3.3V, Parallel mode, AK4393 compatible)
MS0336-E-00
- 32 -
2004/08