AK4396 Datasheet, PDF (31/38 Pages) Asahi Kasei Microsystems – Advanced Multi-Bit 192kHz 24-Bit ΔΣ DAC

ASAHI KASEI
[AK4396]
SYSTEM DESIGN
Figure 12, Figure 13 and Figure 14 show the system connection diagram. Figure 16 , Figure 17 and Figure 18 show the
analog output circuit examples. An evaluation board (AKD4396) is available which demonstrates the optimum layout,
power supply arrangements and measurement results.
Digital
Supply 3.3V
Master Clock
Reset & Power down
64fs
24bit Audio Data
fs
Micro-
controller
Digital Ground
10u 0.1u
+
1 DVSS
2 DVDD
3 MCLK
4 PDN
5 BICK
6 SDATA
7 LRCK
8 CSN
9 CAD0
10 CCLK
11 CDTI
12 DIF0
13 DIF1
14 DIF2
DZFR 28
CAD1 27
DZFL 26
P/S 25
AK4396 ^{VCOM 24}
AOUTL+ 23
AOUTL- 22
AOUTR+ 21
AOUTR- 20
AVSS 19
0.1u
AVDD 18
VREFH 17
0.1u
VREFL 16
TTL 15
0.1u
1+0u
Lch
LPF
Rch
LPF
Lch
Mute
Rch
Mute
10u
+
Analog
+
Supply 5V
10u
Analog Ground
Lch Out
Rch Out
Notes:
- Chip Address = “00”. LRCK = fs, BICK = 64fs.
- Power lines of AVDD and DVDD should be distributed separately from the point with low impedance of regulator
etc.
- AVSS and DVSS must be connected to the same analog ground plane.
- When AOUT drives some capacitive load, some resistor should be added in series between AOUT and
capacitive load.
- All input pins except pull-down/pull-up pins should not be left floating.
Figure 12. Typical Connection Diagram (AVDD=5V, DVDD=3.3V, Serial mode)
MS0336-E-00
- 31 -
2004/08