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AK4396 Datasheet, PDF (24/38 Pages) Asahi Kasei Microsystems – Advanced Multi-Bit 192kHz 24-Bit ΔΣ DAC | |||
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ASAHI KASEI
[AK4396]
 Zero Detection
The AK4396 has channel-independent zeros detect function. When the input data at each channel is continuously zeros
for 8192 LRCK cycles, DZF pin of each channel goes to âHâ. DZF pin of each channel immediately goes to âLâ if input
data of each channel is not zero after going DZF pin âHâ. If RSTN bit is â0â, DZF pins of both channels go to âHâ. DZF
pins of both channels go to âLâ at 4 ~ 5/fs after RSTN bit returns to â1â. If DZFM bit is set to â1â, DZF pins of both
channels go to âHâ only when the input data at both channels are continuously zeros for 8192 LRCK cycles. Zero detect
function can be disabled by DZFE bit. In this case, DZF pins of both channels are always âLâ. DZFB bit can invert the
polarity of DZF pin.
 Soft Mute operation
Soft mute operation is performed at digital domain. When SMUTE pin goes to âHâ or SMUTE bit goes to â1â, the output
signal is attenuated by ââ during ATT_DATA Ã ATT transition time (Table 13) from the current ATT level. When
SMUTE pin is returned to âLâ or SMUTE bit is returned to â0â, the mute is cancelled and the output attenuation gradually
changes to the ATT level during ATT_DATA Ã ATT transition time. If the soft mute is cancelled before attenuating ââ
after starting the operation, the attenuation is discontinued and returned to ATT level by the same cycle. The soft mute is
effective for changing the signal source without stopping the signal transmission.
SM UTE pin or
SM UTE bit
(1)
ATT_Level
A tte n u a tio n
(1)
(3)
-â
GD
GD
(2)
(2)
AOUT
DZF pin
(4)
8192/fs
Notes:
(1) ATT_DATA Ã ATT transition time (Table 13). For example, this time is 1020LRCK cycles (1020/fs)
at ATT_DATA=255 in Normal Speed Mode.
(2) Analog output corresponding to digital input has the group delay (GD).
(3) If the soft mute is cancelled before attenuating ââ after starting the operation, the attenuation is discontinued
and returned to ATT level by the same cycle.
(4) When the input data at each channel is continuously zeros for 8192 LRCK cycles, DZF pin of each channel goes
to âHâ. DZF pin immediately goes to âLâ if input data are not zero after going DZF pin âHâ.
Figure 8. Soft Mute and Zero Detection
 System Reset
The AK4396 should be reset once by bringing PDN pin = âLâ upon power-up. The analog section exits power-down
mode by MCLK input and then the digital section exits power-down mode after the internal counter counts MCLK during
4/fs.
MS0336-E-00
- 24 -
2004/08
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