AKD4683 Datasheet, PDF (21/74 Pages) Asahi Kasei Microsystems – AK4683 Evaluation Board Rev.1

ASAHI KASEI
7-3-2. DAC with PORT B: AK4114 (U10) as external DIR
7-3-2-1. Connection of connector
For digital input, RCA connector J25 (PORTB_RX0) is available.
7-3-2-2. Setting of jumper pin
Setting of interface signal of PORTA: AK4114 (U7) is as follows.
[AKD4683-A]
JP17
JP18
JP11
BICKA OLRCKA ^ILRCKA
JP12
SDTIA
JP13
JP14
JP15
SDTIA1_SEL SDTIA2_SEL SDTIA3_SEL
(open) (open)
(open) (open)
DIR
GND DIR
GND
(GND)
(GND)
DIR
GND
(GND)
Figure 32. JP17 (BICKA), JP18 (OLRCKA), JP11 (ILRCKA), JP12 (SDTIA), JP13 (SDTIA1_SEL),
JP14 (SDTIA2_SEL), JP15 (SDTIA3_SEL)
Setting of interface signal of PORTB: AK4114 (U10) is as follows.
JP23
JP24
BICKB ^LRCKB
JP21
SDTIB_SEL
(short)
(short)
DIR
GND
(DIR)
Figure 33. JP23 (BICKB), JP24 (LRCKB), JP21 (SDTIB_SEL)
When master clock of PORTB: AK4114 (U10): MCKO1 is supplied to AK4683: MCLK2,
setting of master clock is as follows.
JP22
MCLKB_SEL
JP16
MCLKA_SEL
JP19
MCLK_SEL
MCKO1 MCKO2
(MCKO1)
MCKO1 MCKO2
(open)
MCLK2 MCKI
(open)
Figure 34. JP22 (MCLKB_SEL), JP16 (MCLKA_SEL), JP19 (MCLK_SEL)
7-3-2-3. Setting of DIP switch
Set SW4 (PORTB_DIR): 5pin (CM1) to OFF.
Set SW4 (PORTB_DIR): 4pin (CM0) to OFF.
7-3-2-4. Setting of toggle switch
Set SW3 (DIR PORTA) to OFF.
Set SW5 (DIR PORTB) to ON.
Set SW1 (PDN) to OFFË ON.
<KM077504>
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2005/08