AKD4683 Datasheet, PDF (16/74 Pages) Asahi Kasei Microsystems – AK4683 Evaluation Board Rev.1

ASAHI KASEI
[AKD4683-A]
Mode
0
1
2
3
4
5
6
7
DIF2
0
0
0
0
1
1
1
1
DIF1
0
0
1
1
0
0
1
1
DIF0
0
1
0
1
0
1
0
1
DAUX
SDTO
LRCK
I/O
24bit, Left justified 16bit, Right justified H/L O
24bit, Left justified 18bit, Right justified H/L O
24bit, Left justified 20bit, Right justified H/L O
24bit, Left justified 24bit, Right justified H/L O
24bit, Left justified 24bit, Left justified
24bit, I²S
24bit, I²S
H/L O
L/H O
24bit, Left justified 24bit, Left justified
24bit, I²S
24bit, I²S
H/L I
L/H I
Table 4. Audio Interface Format of AK4114
BICK
I/O
64fs O
64fs O
64fs O
64fs O
64fs O
64fs O
64-128fs I
64-128fs I
<Default>
Mode CM1 CM0 UNLOCK PLL
X'tal
Clock source SDTO
0
0
0
-
ON ON (Note1)
PLL
RX
<Default>
1
0
1
-
OFF
ON
X'tal
DAUX
2
1
0
0
ON
ON
1
ON
ON
PLL
RX
X'tal
DAUX
3
1
1
-
ON
ON
X'tal
DAUX
Table 5. Clock Mode (Clock Source)
(Note1) When X’tal is not used on reference clock (XTL0, 1= “1, 1”), this setting is “OFF”
(Note2) Normally, use “Default” setting.
No. OCKS1 OCKS0 MCKO1 MCKO2 X’tal fs (max)
0
0
0
256fs
256fs
256fs 96 kHz ^<Default>
1
0
1
256fs
128fs
256fs 96 kHz
2
1
0
512fs
256fs
512fs 48 kHz
3
1
1
128fs
64fs
128fs 192 kHz
Table 6. Frequency of Master Clock Output
<KM077504>
- 16 -
2005/08