AKD4683 Datasheet, PDF (18/74 Pages) Asahi Kasei Microsystems – AK4683 Evaluation Board Rev.1

ASAHI KASEI
[AKD4683-A]
Setting of interface signal of PORTA: AK4114 (U7) is as follows.
JP17
JP18
JP11
BICKA OLRCKA ^ILRCKA
JP12
SDTIA
JP13
JP14
JP15
SDTIA1_SEL SDTIA2_SEL SDTIA3_SEL
(open)
(open) (open) (open)
DIR
GND DIR
GND DIR
GND
(GND)
(GND)
(GND)
Figure 24. JP17 (BICKA), JP18 (OLRCKA), JP11 (ILRCKA), JP12 (SDTIA), JP13 (SDTIA1_SEL), JP14
(SDTIA2_SEL), JP15 (SDTIA3_SEL)
Setting of interface signal of PORTB: AK4114 (U10) is as follows.
JP23
JP24
BICKB ^LRCKB
JP21
SDTIB_SEL
(open)
(open)
DIR
GND
(GND)
Figure 25. JP23 (BICKB), JP24 (LRCKB), JP21 (SDTIB_SEL)
7-1-3. Setting of DIP switch
SW2 (PORTA_DIR/4683) and SW4 (PORTB_DIR) are “Don’t care”.
7-1-4. Setting of toggle switch
Set SW3 (DIR PORTA) to OFF.
Set SW5 (DIR PORTB) to OFF.
Set SW1 (PDN) to OFFË ON.
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2005/08