DSP16410CG Datasheet, PDF (91/314 Pages) Agere Systems – DSP16410CG Digital Signal Processor

Data Sheet
May 2003
DSP16410CG Digital Signal Processor
4 Hardware Architecture (continued)
4.13 Direct Memory Access Unit (DMAU) (continued)
4.13.6 Memory-to-Memory Transfer Channels (MMT) (continued)
If source look-ahead is enabled, the DMAU performs the same steps as above except that it initially repeats steps
2—4 multiple times in a pipelined manner. It then performs reads and writes to the source and destination blocks
as access cycles become available. It is strongly recommended that the user enable source look-ahead. See
Section 4.14.7.4 on page 131 for a performance comparison.
The DMAU’s control and address registers determine the data size and location supported by a particular channel
and reflect the status of the request. These MMT channel registers are described in Table 49 on page 91 with
additional detail provided in Section 4.13.2.
Table 49. MMT-Specific Memory-Mapped Registers
Register
SADD〈4—5〉
SCNT〈4—5〉
Type
Source
Address
Source
Counter
Size
Description
32-bit Prior to each MMT block move, the program must initialize the corresponding
SADD〈4—5〉 register with the starting address in memory for the source block (read
data). The DMAU updates the register with the address of the next memory location to
be read by the specified MMT channel as the block move proceeds. Table 37 on
page 77 describes the bit fields of SADD〈4—5〉.
20-bit This register contains the source row and column counter for the corresponding
channel. The DMAU updates the register as the block move proceeds and automatically
clears the register upon the completion of the block move. The source row (SROW) is
encoded in SCNT〈4—5〉[19:7], and the source column (SCOL) is encoded in
SCNT〈4—5〉[6:0].
DADD〈4—5〉
DCNT〈4—5〉
Destination
Address
Destination
Counter
Note: SCNT〈4—5〉 are not cleared by a reset of the DMAU channel via the DMCON1
register (Table 32 on page 72). Before an MMT channel can be used, the pro-
gram must clear the corresponding SCNT〈4—5〉 register after a DSP16410CG
device reset. Otherwise, the value of this register is undefined.
32-bit Prior to each MMT block move, the program must initialize the corresponding
DADD〈4—5〉 register with the starting address in memory for the destination block (write
data). The DMAU updates the register with the address of the next memory location to
be written by the specified MMT channel as the block move proceeds. Table 37 on
page 77 describes the bit fields of DADD〈4—5〉.
20-bit This register contains the destination row and column counter for the corresponding
channel. The DMAU updates the register as the block move proceeds and automatically
clears the register upon the completion of the block move. The destination row (DROW)
is encoded in DCNT〈4—5〉[19:7] and the destination column (DCOL) is encoded in
DCNT〈4—5〉[6:0].
LIM〈4—5〉
CTL〈4—5〉
Limit
Control
Note: DCNT〈4—5〉 are not cleared by a reset of the DMAU channel via the DMCON1
register (Table 32 on page 72). Before an MMT channel can be used, the user
program must clear the corresponding DCNT〈4—5〉 register after a
DSP16410CG device reset. Otherwise, the value of this register is undefined.
20-bit The user programs LIM〈4—5〉 with the last row count and the last column count for both
the source and destination blocks for the corresponding channel. The last row count is
the number of rows minus one and is encoded in the LASTROW field (LIM〈4—5〉[19:7]).
The last column count is the number of columns minus one and is encoded in the LAST-
COL field (LIM〈4—5〉[6:0]). Typically, LASTCOL is zero for a block move.
16-bit CTL〈4—5〉 controls interrupt generation for both the source and destination block
moves.
The two 16-bit DMAU master control registers, DMCON0 and DMCON1, influence the operation of the MMT chan-
nels. The 32-bit DMAU status register, DSTAT, reflects the status of any MMT transfer. The bit field definition of
the DMAU control and status registers is given in Section 4.13.2.
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