DSP16410CG Datasheet, PDF (210/314 Pages) Agere Systems – DSP16410CG Digital Signal Processor

DSP16410CG Digital Signal Processor
Data Sheet
May 2003
6 Software Architecture (continued)
6.1 Instruction Set Quick Reference (continued)
Table 129. Instruction Set Summary
Instruction
Multiply/Accumulate (MAC) Group
F1
Y
F1
x〈h,l〉 = Y
F1
y〈h,l〉 = Y
F1
a 〈h,l〉 = Y
F1
Y = y〈h,l〉
F1
Y = aT〈h,l〉
F1 yh = aTh
F1
yh = Y
if CON F1E
F1E yh,l = aTEh,l
F1E aTEh,l = yh,l
F1E y = aE_Ph
F1E aE_Ph = y
F1E
xh,l = YE
F1E
yh,l = YE
F1E
aTEh,l = YE
F1E
aE_Ph = YE
F1E
YE = xh,l
F1E
YE = yh,l
F1E
YE = aTEh,l
F1E
YE = aE_Ph
F1E yh = *r0 r0 = rNE + jhb
F1E
YE
F1E
F1E
F1E
F1E y = aE_Ph
F1E yh = aTEh
F1E aTEh = yh
F1E
yh,l = YE^‡
F1E
yh,l = YE
F1E
YE = yh,l
F1E
yh = YE^‡
F1E
YE = a6_7h
F1E
YE = a6h^‡
F1E
YE = a6h^‡
xh = X
xh = X
xh,l = XE
aTEh,l = XE
aE_Ph = XE
x h = XE
x h = XE
xh = XE
a4h = XE
xh = XE
xh = XE
a4_5h = XE
xh = XE
xh = XE
a4h = XE
Flags
szlme
Cycles
Out
In
Words
szlm–
1
1
1
szlm–
szlm–
szlm–
szlm–
szlm–
szlm– 1+XC^†
szlm–
szlme
1
1
2
szlme
szlme
szlme
szlme
szlme
szlme
szlme
szlme
szlme
szlme
szlme
szlme
szlme
szlme
szlme 1+XC^†
szlme
szlme
szlme
szlme
szlme
szlme
szlme
szlme
szlme
szlme
szlme
szlme
† XC is one cycle if XAAU contention occurs and zero cycles otherwise. XAAU contention occurs frequently for these instruc-
tion types and can only be avoided by use of the cache.
‡ For this transfer, the postincrement options *rME and *rME–– are not available for double-word loads.
§ The – (40-bit subtraction) operation is encoded as aDE =aSE +IM16 with the IM16 value negated.
†† For conditional branch instructions, the execution time is two cycles if the branch is not taken.
‡‡ The instruction performs the same function whether or not near (optional) is included.
§§ Not including the N instructions.
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