DSP16410CG Datasheet, PDF (282/314 Pages) Agere Systems – DSP16410CG Digital Signal Processor

DSP16410CG Digital Signal Processor
11 Timing Characteristics and Requirements (continued)
11.7 Interrupt and Trap
ECKO^†
INT^‡
t21
t22
† ECKO reflects CLK, i.e., ECON1[1:0] = 1.
‡ INT is one of INT[3:0] or TRAP.
Figure 72. Interrupt and Trap Timing Diagram
Table 192. Timing Requirements for Interrupt and Trap
Abbreviated Reference
Parameter
Min
t21
Interrupt Setup (high to low)
8
t22
INT/TRAP Assertion Time (high to low)
2T^†
† T = internal clock period (CLK).
Data Sheet
May 2003
5-4018(F).g
Max
Unit
—
ns
—
ns
282
Agere Systems—Proprietary
Agere Systems Inc.
Use pursuant to Company instructions