DSP16410CG Datasheet, PDF (45/314 Pages) Agere Systems – DSP16410CG Digital Signal Processor

Data Sheet
May 2003
DSP16410CG Digital Signal Processor
4 Hardware Architecture (continued)
4.6 Triport Random-Access Memory
(TPRAM) (continued)
The core’s X and Y ports and the DMAU’s Z port can
access separate modules within a TPRAM simulta-
neously with no wait-states incurred by the core. If the
same module of TPRAM is accessed from multiple
ports simultaneously, the TPRAM automatically
sequences the accesses in the following priority order:
X port (instruction/coefficient), Y port (data), then Z port
(DMAU). This sequencing can cause the core to incur
a conflict wait-state. Because the core must complete
any consecutive accesses to a module of TPRAM
before the DMAU can access that module, the DMAU
can be blocked from accessing that module for a signif-
icant number of cycles.
4.7 Shared Local Memory (SLM)
Each core, the DMAU, and the PIU can access SLM
(shared local memory) through the SEMI and the sys-
tem buses (SAB and SDB). SLM is a 2 Kword block
located in the internal I/O memory component. SLM
supports both 16-bit and aligned 32-bit accesses, but
not 32-bit misaligned accesses.
The SEMI controls access to the SLM, which is subject
to wait-state and contention penalties; see
Section 4.14.7.1 on page 126 for details. Because
access to the SLM is subject to wait-state and conten-
tion penalties, it is not an efficient method for transfer-
ring large blocks of data between the cores. (An
efficient method is to use the DMAU memory-to-mem-
ory (MMT) channel.)
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