DSP16410CG Datasheet, PDF (263/314 Pages) Agere Systems – DSP16410CG Digital Signal Processor

Data Sheet
May 2003
DSP16410CG Digital Signal Processor
9 Device Characteristics
9.1 Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are
absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in
excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for
extended periods can adversely affect device reliability.
External leads can be bonded and soldered safely at temperatures of up to 235 °C.
Table 174. Absolute Maximum Ratings for Supply Pins
Parameter
Voltage on VDD1 with Respect to Ground
Voltage on VDD1A with Respect to Ground
Voltage on VDD2 with Respect to Ground
Voltage Range on Any Signal Pin
Junction Temperature (TJ)
Storage Temperature Range
Min
–0.5
–0.5
–0.5
VSS – 0.3
–40
–40
Max
2.0
2.0
4.0
VDD2 + 0.3
4.0
120
150
Unit
V
V
V
V
°C
°C
9.2 Handling Precautions
Although electrostatic discharge (ESD) protection circuitry has been designed into this device, proper precautions
must be taken to avoid exposure to ESD and electrical overstress (EOS) during all handling, assembly, and test
operations. Agere employs both a human-body model (HBM) and a charged-device model (CDM) qualification
requirement in order to determine ESD-susceptibility limits and protection design evaluation. ESD voltage thresh-
olds are dependent on the circuit parameters used in each of the models, as defined by JEDEC's JESD22-A114
(HBM) and JESD22-C101 (CDM) standards.
Table 175. Minimum ESD Voltage Thresholds
Device
DSP16410CG
Minimum HBM Threshold
2000 V
Minimum CDM Threshold
1000 V
9.3 Recommended Operating Conditions
Table 176. Recommended Operating Conditions
Maximum
Internal Clock
(CLK) Frequency
195 MHz
Minimum
Internal Clock
(CLK) Period T
5.0 ns
Junction
Temperature TJ (°C)
Min
Max
–40
120
Supply Voltage
VDD1, VDD1A (V)
Min
Max
1.5
1.65
Supply Voltage
VDD2 (V)
Min
Max
3.0
3.6
The ratio of the instruction cycle rate to the input clock frequency is 1:1 without the PLL and
((M + 2)/((D + 2) * f(OD))):1 with the PLL selected. The maximum input clock (CKI pin) frequency when the
PLL is not selected as the device clock source is 50 MHz. The maximum input clock frequency is 40 MHz
when the PLL is selected.
Agere Systems Inc.
Agere Systems—Proprietary
263
Use pursuant to Company instructions