DSP16410CG Datasheet, PDF (281/314 Pages) Agere Systems – DSP16410CG Digital Signal Processor

Data Sheet
May 2003
DSP16410CG Digital Signal Processor
11 Timing Characteristics and Requirements (continued)
11.6 JTAG
TCK0, TCK1 ^VIH
VIL
TMS0, TMS1 ^VIH
VIL
TDI0, TDI1 ^VIH
VIL
VOH
TDO0, TD01
VO L
t155
t12
t13
t14
t15
t156
t16
t17
t18
t19
t20
Figure 71. JTAG I/O Timing Diagram
Table 190. Timing Requirements for JTAG I/O
Abbreviated Reference
t12
t13
t14
t155
t156
t15
t16
t17
t18
Parameter
TCK Period (high to high)
TCK High Time (high to low)
TCK Low Time (low to high)
TCK Rise Transition Time (low to high)
TCK Fall Transition Time (high to low)
TMS Setup Time (valid to high)
TMS Hold Time (high to invalid)
TDI Setup Time (valid to high)
TDI Hold Time (high to invalid)
Table 191. Timing Characteristics for JTAG I/O
Abbreviated Reference
t19
t20
Parameter
TDO Delay (low to valid)
TDO Hold (low to invalid)
5-4017(F).d
Min
Max
Unit
50
—
ns
22.5
—
ns
22.5
—
ns
0.6
—
V/ns
0.6
—
V/ns
7.5
—
ns
5
—
ns
7.5
—
ns
5
—
ns
Min
Max
Unit
—
15
ns
0
—
ns
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