DSP16410CG Datasheet, PDF (151/314 Pages) Agere Systems – DSP16410CG Digital Signal Processor

Data Sheet
May 2003
DSP16410CG Digital Signal Processor
4 Hardware Architecture (continued)
4.15 Parallel Interface Unit (PIU) (continued)
4.15.7 PIU Interrupts
A core can issue an interrupt to the host by setting the
PINT field (PCON[3]—see Table 73 on page 134). If
this field is initially cleared and the core sets it, the PIU
asserts (high) the PINT pin. The host must clear this
field after servicing the PINT request to allow a core to
request a subsequent interrupt. It clears the field by
writing 1 to it.
The host can issue an interrupt to the cores by setting
the HINT field (PCON[4]—see Table 73 on
page 134). If this field is initially cleared and the host
sets it, the PIU asserts the PHINT interrupt to the
cores. The interrupted core’s service routine must
clear this field after servicing the PHINT request to
allow the host to request a subsequent interrupt. It
clears the field by writing 1 to it. See Section 4.4 for
more information on interrupts.
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