LU5X34F Datasheet, PDF (9/26 Pages) Agere Systems – Quad Gigabit Ethernet Transceiver

Preliminary Data Sheet
July 2000
LU5X34F
Quad Gigabit Ethernet Transceiver
Input/Output Information (continued)
Table 3a. Pinout—Channel A I/O
Name
TXA9
TXA8
TXA7
TXA6
TXA5
TXA4
TXA3
TXA2
TXA1
TXA0
RXA9
RXA8
RXA7
RXA6
RXA5
RXA4
RXA3
RXA2
RXA1
RXA0
TXCLKA
Pin
I/O
A14
Input
C13
D12
B14
A15
D13
C14
B15
A16
A17
B11
Output
C10
A11
B10
A10
B9
A9
C9
A8
B8
C12
Input
RXCLK0A
RXCLK1A
ENCDETA
COMDETA
EWRAPA
LCKREFNA
HDINAP,
HDINAN
HDOUTAP,
HDOUTAN
LDSTA
C11
B12
E2
A12
D1
E1
D15, E14
F14, E15
F3
Output
Output
Input
Output
Input
Input
Input
Output
Input
Level
TTL/
CMOS
Description
Channel A, Transmit Data [9:0].
Parallel input bits [9:0], one 10-bit, 8b/10b encoded
data byte, clocked-in on the rising edge of TXCLKA.
TXA0 is the LSB.
TTL/
CMOS
Channel A, Receive Data [9:0].
Parallel output bits [9:0], one 10-bit data type, clocked-
out on the alternate rising edge of RXCLK0A,
RXCLK1A. RXA0 is the LSB.
TTL/
CMOS
TTL/
CMOS
TTL/
CMOS
TTL/
CMOS
TTL/
CMOS
TTL/
CMOS
TTL/
CMOS
PECL
Transmit Clock (100 MHz—125 MHz).
Used to latch TXA[9:0] data into the LU5X34F.
Synchronous with REFCLK(N)
Channel A, Receive Byte-Align Clock 0.
Channel A, Receive Byte-Align Clock 1.
Channel A, Enable Comma Detect A.
Channel A, Byte-Aligned Comma A.
Channel A, Loopback at Serial I/O A.
Channel A, Lock Receiver to Clock.
Channel A, Differential Serial Inputs.
PECL _{Channel A, Differential Serial Outputs.}
TTL/ _{Channel A, Load Test[5:1] Inputs.}
CMOS
Lucent Technologies Inc.
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