LU5X34F Datasheet, PDF (10/26 Pages) Agere Systems – Quad Gigabit Ethernet Transceiver

LU5X34F
Quad Gigabit Ethernet Transceiver
Preliminary Data Sheet
July 2000
Input/Output Information (continued)
Table 3b. Pinout—Channel B I/O
Name
TXB9
TXB8
TXB7
TXB6
TXB5
TXB4
TXB3
TXB2
TXB1
TXB0
RXB9
RXB8
RXB7
RXB6
RXB5
RXB4
RXB3
RXB2
RXB1
RXB0
TXCLKB
Pin
I/O
A4
Input
B5
C6
A5
B6
A6
C7
D7
B7
A7
B3
Output
A2
A1
B1
C2
D3
E4
C1
D2
F4
D6
Input
RXCLK0B
RXCLK1B
ENCDETB
COMDETB
EWRAPB
LCKREFNB
HDINBP,
HDINBN
HDOUTBP,
HDOUTBN
LDSTB
A3
B4
G3
C4
F2
F1
F15, E17
G14, G15
G4
Output
Output
Input
Output
Input
Input
Input
Output
Input
Level
TTL/
CMOS
Description
Channel B, Transmit Data [9:0].
Parallel input bits [9:0], one 10-bit, 8b/10b encoded
data byte, clocked-in on the rising edge of TXCLKB.
TXB0 is the LSB.
TTL/
CMOS
Channel B, Receive Data [9:0].
Parallel output bits [9:0], one 10-bit data type, clocked-
out on the alternate rising edge of RXCLK0B,
RXCLK1B. RXB0 is the LSB.
TTL/
CMOS
TTL/
CMOS
TTL/
CMOS
TTL/
CMOS
TTL/
CMOS
TTL/
CMOS
TTL/
CMOS
PECL
Transmit Clock (100 MHz—125 MHz).
Used to latch TXB[9:0] data into the LU5X34F.
Synchronous with REFCLK(N)
Channel B, Byte-Align Clock 0.
Channel B, Byte-Align Clock 1.
Channel B, Enable Comma Detect.
Channel B, Byte-Aligned Comma.
Channel B, Loopback at Serial I/O.
Channel B, Lock Receiver to Clock.
Channel B, Differential Serial Inputs.
PECL Channel B, Differential Serial Outputs.
TTL/ Channel B, Load TEST[5:1] inputs.
CMOS
10
Lucent Technologies Inc.