LU5X34F Datasheet, PDF (6/26 Pages) Agere Systems – Quad Gigabit Ethernet Transceiver

LU5X34F
Quad Gigabit Ethernet Transceiver
Functional Description (continued)
Block Diagrams
Preliminary Data Sheet
July 2000
LPWR RESET
OLREF OLRVS
HDINAP
HDINAN
2
HDOUTAP 2
HDOUTAN
HDINBP ₂
HDINBN
HDOUTBP ²
HDOUTBN
REFCLK
2
REFCLKN
TRANSCEIVER A
TRANSCEIVER B
ANALOG PLL
HDINCP ₂
HDINCN
2
HDOUTCP
HDOUTCN
HDINDP ₂
HDINDN
HDOUTDP ²
HDOUTDN
TRANSCEIVER C
TRANSCEIVER D
TEST CIRCUITS
RXA[9:0]
TXA[9:0]
RXB[9:0]
TXB[9:0]
TEST[5:1]
LDST[A:D]
BYPPLL
RXCLK0[A:D]
RXCLK1[A:D]
RXC[9:0]
TXC[9:0]
RXD[9:0]
TXD[9:0]
* Synchronous with REFCLK(N).
Figure 1. LU5X34F Quad Gigabit Ethernet Transceiver Block Diagram
5-8808(F)
6
Lucent Technologies Inc.