LU5X34F Datasheet, PDF (5/26 Pages) Agere Systems – Quad Gigabit Ethernet Transceiver

Preliminary Data Sheet
July 2000
LU5X34F
Quad Gigabit Ethernet Transceiver
Functional Description (continued)
Powerup Sequence
The power ramp time for the LU5X34F is specified at
VDD > 2.7 V within 20 µs of start-up. Once 2.7 V is
reached, the device is held in reset for 15 µs—70 µs.
The REFCLK must be active and within specification at
this point and remain active while the device is pow-
ered up, unless in Reset.
When signals RESET, BYPPLL, and LPWR are all low,
the following start-up sequence occurs:
1. 0 µs—32 µs, the analog PLL is held at minimum fre-
quency to allow dc bias to settle.
2. 32 µs—262 µs, the analog PLL has locked-in and
receiver analog circuits start to lock-in.
3. 262 µs—326 µs, the receiver analog circuits are
locked; receiver starts to lock onto incoming data.
4. After 358 µs, the receiver is locked onto incoming
data and can be viewed at the parallel output ports.
The comma-detect circuit is enabled at this point,
allowing byte alignment if ENCDET = 1.
If LCKREFN goes low after the 358 µs, the receiver will
sit idle. When LCKREFN goes high, the receiver will be
locked onto data after 2 µs.
Sleep Mode
The LU5X34F has a sleep mode that is activated by
enabling LPWR. In this mode, a divided-down version
of the REFCLK is used to refresh the dynamic circuits
within the transceiver. The PLL is powered down in this
mode also. LCKREFN can also be activated to reduce
the power even further. Note that complete powerdown
for IDDQ testing is not supported due to the dynamic
logic used in the high-speed sections of the trans-
ceiver. The lock-in sequence timing is needed when
coming out of sleep mode.
Device Reset
The RESETN input to the device is active-low. When
activated with a pulse duration of 1 µs, the RESETN sig-
nal globally resets the device and the following is per-
formed:
1. The single analog PLL is forced to operate at the mini-
mum frequency possible for its VCO. The PLL will not
be locked in this condition.
2. The HDOUTP, HDOUTN outputs are forced to a
PECL logic 0.
3. The deserializer clocks, but input data at HDINP,
HDINN is ignored and the RX[9:0] signals remain in
their previous state.
4. The phase interpolation/selection circuits are deacti-
vated and the selected phase is reset.
5. The receiver digital low-pass filter in the DPLL is reset.
Normally, a reset is not necessary for correct operation,
although a reset can aid rapid lock-in of the internal
PLL circuitry. This active-low pin is internally pulled
high.
Lucent Technologies Inc.
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