LU5X34F Datasheet, PDF (13/26 Pages) Agere Systems – Quad Gigabit Ethernet Transceiver

Preliminary Data Sheet
July 2000
LU5X34F
Quad Gigabit Ethernet Transceiver
Input/Output Information (continued)
Table 3e. Pinout—Common I/O
Name
OLREF
OLRVS
LPWR
RESETN
TEST5*
TEST4*
TEST3*
TEST2*
TEST1*
BYPPLL
REFCLK,
REFCLKN
Pin
K16
K17
J3
G2
J2
H1
H2
G1
H3
J1
K1, K2
I/O
Input/
Output
Input/
Output
Input
Input
Input/
Output
Input
Input
Input
Input
Input
Input
* For related information, see Table 18, Test Modes.
Table 3f. Pinout—Power I/O
Level
Description
Analog PECL Level Set Resistor Terminal 1.
Analog PECL Level Set Resistor Terminal 2.
TTL/
CMOS
TTL/
CMOS
TTL/
CMOS
TTL/
CMOS
TTL/
CMOS
TTL/
CMOS
TTL/
CMOS
TTL/
CMOS
PECL or
TTL/
CMOS
Device Low-Power Mode.
Device Reset (Active-Low).
Global Test Control Input/Output.
Local Test Control Input.
Local Test Control Input.
Local Test Control Input.
Local Test Control Input.
Test Control, PLL Bypass Mode.
Reference Clock Input (100 MHz—125 MHz).
Used by the transmitter PLL to generate the
1.0 Gbits/s— 1.25 Gbits/s serial data; has a +100 ppm
tolerance requirement.
Name
VDD
VDDP
VDDTX
VDDR
VSS
VSSP
VSST
VSSRX
Pin
D5, D8, D10, B13, H4, K4, P8, P10
G17, H16
D16, D17, F17, G16, L15, N16, N14, T17,
H14, K14
B2, C3, D4, D9, H8, H9, H10, J4, J8, J9, J10,
K8, K9, K10, P4, P9, P14, R3, R15, T2, T16
H15, H17
B16, C15, D14, J14
C16, C17, E16, F16, K15, L14, P17, R17
Description
Device Digital Power.
PLL Power.
High-Speed Analog Transmitter Power.
High-Speed Analog Receiver Power.
Device Digital Ground.
PLL Ground.
High-Speed Analog Transmitter Ground.
High-Speed Analog Receiver Ground.
Lucent Technologies Inc.
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