LU5X34F Datasheet, PDF (12/26 Pages) Agere Systems – Quad Gigabit Ethernet Transceiver

LU5X34F
Quad Gigabit Ethernet Transceiver
Preliminary Data Sheet
July 2000
Input/Output Information (continued)
Table 3d. Pinout—Channel D I/O
Name
TXD9
TXD8
TXD7
TXD6
TXD5
TXD4
TXD3
TXD2
TXD1
TXD0
RXD9
RXD8
RXD7
RXD6
RXD5
RXD4
RXD3
RXD2
RXD1
RXD0
TXCLKD
Pin
I/O
R10
Input
T10
U10
R10
U9
T9
U8
T8
U7
R8
R12
Output
T13
U14
P12
R13
T14
U15
P13
R14
T15
T11
Input
RXCLK0D
RXCLK1D
ENCDETD
COMDETD
EWRAPD
LCKREFND
HDINDP,
HDINDN
HDOUTDP,
HDOUTDN
LDSTD
U12
R11
M1
U13
L3
N1
N15, P16
R16, P15
M2
Output
Output
Input
Output
Input
Input
Input
Output
Input
Level
TTL/
CMOS
Description
Channel D, Transmit Data [9:0].
Parallel input bits [9:0], one 10-bit, 8b/10b encoded
data byte, clocked-in on the rising edge of TXCLKD.
TXD0 is the LSB.
TTL/
CMOS
Channel D, Receive Data [9:0].
Parallel output bits [9:0], one 10-bit data type, clocked-
out on the alternate rising edge of RXCLK0D,
RXCLK1D. RXD0 is the LSB.
TTL/
CMOS
TTL/
CMOS
TTL/
CMOS
TTL/
CMOS
TTL/
CMOS
TTL/
CMOS
TTL/
CMOS
PECL
Transmit Clock (100 MHz—125 MHz).
Used to latch TXD[9:0] data into the LU5X34F.
Synchronous with REFCLK(N)
Channel D, Byte-Align Clock 0.
Channel D, Byte-Align Clock 1.
Channel D, Enable Comma Detect.
Channel D, Byte-Aligned Comma.
Channel D, Loopback at Serial I/O.
Channel D, Lock Receiver to Clock.
Channel D, Differential Serial Inputs.
PECL Channel D, Differential Serial Outputs.
TTL/ Channel D, Load Test[5:1] Inputs.
CMOS
12
Lucent Technologies Inc.