CT2553 Datasheet, PDF (32/36 Pages) Aeroflex Circuit Technology – CT2553 / 2554 / 2555 / 2556 Advanced Integrated MUX (AIM) Hybrid FOR MIL-STD-1553

Table 7A – CT2553 Pin Function Table (78 Pin DIP) (continued)
Pin
Name
45 D09
46 D11
47 D13
48 D15
49 RTAD3
50 RTAD2
51 RTADP
52 SA/MC-2
53 SA/MC-4
54 SA/MC-3
55 THIS-RT
56 RTPARERR
57 T/R
58 +5VB
59 TX/RX-B
60 A00
61 A02
62 A04
63 A06
64 A08
65 A10
66 A12
67 A14
68 MEMWR
69 MEMENA-IN
70 INCMD
71 MSTRCLR
72 INT
73 IOEN
74 SELECT
75 READYD
76 TAGEN
77 +5VA
78 TX/RX-A
I_IH(µA) I_IL(mA) I_OH(µA) I_OL (mA)
Description
(5)
-0.4 -400
(5)
-0.4 -400
(5)
-0.4 -400
(5)
-0.4 -400
(5)
-0.4
-
(5)
-0.4
-
(5)
-0.4
-
-
-
-400
-
-
-400
-
-
-400
-
-
-400
-
-
-400
-
-
-400
-
-
-
-
-
-
(5)
-0.4 -400
(5)
-0.4 -400
(5)
-0.4 -400
(5)
-0.4 -400
(5)
-0.4 -400
(5)
-0.4 -400
(5)
-0.4 -400
(5)
-0.4 -400
-
-
-400
±20 ±0.02
-
-
-
-400
(6)
-0.7
-
-
-
-400
-
-
-400
(6)
-0.7
-
-
-
-400
-
-
-400
-
-
-
-
-
-
3.6 I/O Data Bus Bit 9.
3.6 I/O Data Bus Bit 11.
3.6 I/O Data Bus Bit 13.
3.6 I/O Data Bus Bit 15 (MSB).
- Remote Terminal Address Bit 3.
- Remote Terminal Address Bit 2.
- Remote Terminal Address Parity input.
2.0 Subaddress/Mode Command Bit 2. B8 (MSB) counter.
2.0 Subaddress/Mode Command Bit 4.
2.0 Subaddress/Mode Command Bit 3.
2.0 Logic 0 pulse indicates receipt of a valid command word which contains
the Remote Terminal address equivalent to the RTADO-RTAD4 inputs.
2.0 RTU (address) Parity Error. Logic 0 indicates RTU address parity (odd
parity: RTADO-RTAD4, RTADP) has been violated.
2.0 Transmit/Receive 1553 data. Latched T/R bit from current command
word.
- +5V power supply connection for the B channel transceiver.
- Transmit/Receive transceiver-B. Inverted I/O to coupling transformer
that connects to channel B of the 1553 Bus.
3.6 Address Bit 0 (LSB).
3.6 Address Bit 2.
3.6 Address Bit 4.
3.6 Address Bit 6.
3.6 Address Bit 8.
3.6 Address Bit 10.
3.6 Address Bit 12.
3.6 Address Bit 14.
4.0 Memory Write. Output pulse to write data into memory.
- Memory Enable In. Enables internal RAM only; connect directly to
MEMENA-OUT.
2.0 In Command. Indicates BC or RTU currently in message transfer
sequence.
- Master Clear. Power-on reset from CPU.
4.0 Interrupt. Interrupt pulse line to CPU.
4.0 Input/Output Enable. Output to enable external hybrid to the
address/data bus.
- Select. Input from the CPU. When active, selects CT2553 for operation.
4.0 Ready Data. When active indicates data has been received from, or is
available to, the CPU.
4.0 Tag Enable. Enables an external time to counter for transferring the
time tag word into memory.
- +5V input/power supply for channel A transceiver.
- Transmit/Receive transceiver-A. Inverted I/O to the coupling
transformer that connects to the A channel of the 1553 Bus.
1. I_IH is specified at: V_CC = 5.5V, V_IH = 2.7V.
2. I_IL is specified at: V_CC = 5.5V, V_IL = 0.4V.
3. I_OH is specified at: V_CC = 4.5V, V_IH = 2.4V.
4. I_OL is specified at: V_CC = 4.5V, V_IH = 0.4V.
5. Internal Pull-up Resistor = 30K Ohms, typ.
6. Internal Pull-up Resistor = 16K Ohms, typ.
7. Pin 13 = B6, Pin 15 = B7 and Pin 52 = B8 (MSB). B6, B7 and B8 are the MSB lines of an 8 BIT Counter used in the BC and MT
mode to count 32 WORD TRANSFERS to memory (16 words received off the bus) for a total of 128 DATA and Tag words (in
MT mode). (See pages 19 & 20 for discussion.)
Aeroflex Circuit Technology
32
SCDCT2553 REV B 8/6/99 Plainview NY [phone]