CT2553 Datasheet, PDF (28/36 Pages) Aeroflex Circuit Technology – CT2553 / 2554 / 2555 / 2556 Advanced Integrated MUX (AIM) Hybrid FOR MIL-STD-1553

16MHz Clock
(Internal)
STRBD
SELECT
IOEN
READYD
MEM/REG
RD/WR
MEMENA-OUT
MEMWR
A15-A00
D15-D00
See Note 1
tz
tr
See Note 2
td1
td2
tpw1
td3
tpw2
RAM ADDRESS VALID
RAM DATA VALID
NOTE:
1. STRBD to IOEN (low) delay is two clock cycles. If contention occurs, delay is two clock cycles following release of bus.
2. CPU must release STRBD within 1.5µs of IOEN going active. READYD will go away within one clock cycle maximum.
SYMBOL
td1
td2
tpw1
td3
tpw2
tr
tz
CPU Writes to Ram
DESCRIPTION
MIN
READYD low delay (CPU Handshake)
-
IOEN high delay (CPU Handshake)
-
READYD pulse width (CPU Handshake)
50
CPU MEMWR low delay
-
CPU MEMWR low pulse width
70
READYD to STRBD release
-
(SELECT • STRBD) to IOEN
-
MAX
150
20
-
120
-
1.37
1.8
UNITS
ns
ns
ns
ns
ns
µs
µs
Aeroflex Circuit Technology
Figure 31 – CPU Writes to RAM Timing
28
SCDCT2553 REV B 8/6/99 Plainview NY [phone]