CT2553 Datasheet, PDF (10/36 Pages) Aeroflex Circuit Technology – CT2553 / 2554 / 2555 / 2556 Advanced Integrated MUX (AIM) Hybrid FOR MIL-STD-1553

CPU TO REGISTER OPERATIONS. The CPU
selects a register by asserting MEM/REG low and
A2 to a logic 0 (for internal registers) or logic 1 (for
external registers) with A0 and A1 indicating the
appropriate register address (See Figures 28-32).
The signals EXTEN and EXTLD are used to
access the external registers.
15
RTU/BC
MT
CURRENT AREA B/A
STOP ON ERROR
BIT NAME
87
0
111111 11
SUBSYSTEM FLAG
SERVICE REQUEST
BUSY
DB ACCEPT
DEFINITION
CONFIGURATION REGISTER. The Configuration
Register is a 16-bit read/write register used to
define the 1553 operating mode (BC, RTU, or MT);
define selectable 1553 Status Word bits (RTU
only); select stop-on-error option; and support the
double buffering scheme (See Figure 11).
SUBYSTEM FLAG
SERVICE REQUEST
BUSY
DB ACCEPT
STOP ON ERROR
CURRENT AREA B/A
RTU/BC
Sets/resets 1553 Status Word flag.
Sets/resets 1553 Status Word flag.
Sets/resets 1553 Status Word flag.
Sets/resets 1553 Status Word flag.
BC will halt message transfer after
completing current EOM cycle.
Selects Current Area Pointers.
RTU or BC-MT Operation Select.
BIT15
0
0
1
1
BIT 14
0
1
0
1
Operation
BC
MT
RTU
Illegal
Note: A logic 0 causes the corresponding bit within the RTU’s status
word to be set to a logic 1.
Figure 11 – Configuration Register
INTERRUPT MASK REGISTER (BC/RTU). This
register is a 16-bit read/write register used to
enable/mask interrupt conditions. If an interrupt
condition occurs and the corresponding Interrupt
Register bit has been enabled (set to logic 1) pin
72, INT will be pulsed low during the respective
End of Message (EOM) cycle (See Figure 12). Not
Used bit locations can optionally be used for
storing user flags.
15
987
43210
1111111
BC EOM
NOT
USED
FORMAT ERROR/STATUS SET
NOT USED
EOM
START/RESET REGISTER. This write-only
register is used to reset the CT2553 and to start
the BC and MT operations, as illustrated in
Figure 13.
15
987
43210
NOT USED
CONTROLLER START
RESET
INTERRUPT
DEFINITION
EOM
FORMAT
ERROR/
STATUS SET
BC EOM
End of message. Set by CT2553 in BC or
RTU mode following each 1553 transfer
(regardless of validity).
Set if one of the following occurs:.
Loop Test Failure: Received word does
not match last word transmitted.
Message Error: Received message
contained a violation of any of the 1553
message validation criteria (parity, sync,
manchester encoding, bit/word count, etc.)
Time-Out: Expected transmission was
not received during the allotted time.
Status Set: Received Status Word
contained status bit(s) set or address error.
Bus Controller End of Message. Set by the
CT2553 following transmission of all
messages within the current Message Block
(Current area message count = FFFF).
START
RESET
BIT 1
1
0
BIT 0
0
1
BIT NAME
DEFINITION
CONTROLLER
START
RESET
Issued by the CPU to start
message block transmission (BC
Operation) or to begin reception of
1553 messages (MT Operation).
Issued by the CPU to place the
CT2553 in the power-on condition;
(1) aborts 1553 transfers currently
in progress, and (2) resets
Configuration and Interrupt Mask
Register bits (logic 0).
Figure 12 – Interrupt Mask Register
Figure 13 – Start/Reset Register
Aeroflex Circuit Technology
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SCDCT2553 REV B 8/6/99 Plainview NY [phone]