CT2553 Datasheet, PDF (25/36 Pages) Aeroflex Circuit Technology – CT2553 / 2554 / 2555 / 2556 Advanced Integrated MUX (AIM) Hybrid FOR MIL-STD-1553

16MHz Clock
(Internal)
STRBD
SELECT
IOEN
READYD
MEM/REG
RD/WR
See Note 1
td1
tz
See Note 2
td8
tr
td2
tpw1
A02
A01
A00
SSFLAG, SSBUSY, SVCRQST
DBAC, RTU/BC, MT, CTLOUT B/A
td7
DATA LATCHED
Configuration Register Only
D15-D00
DATA VALID
td9
NOTE:
1. STRBD to IOEN (low) delay is two clock cycles. If contention occurs, delay is two clock cycles following release of bus.
2. CPU must release STRBD within 1.5µs of IOEN going active. READYD will go away within one clock cycle maximum.
SYMBOL
td1
td2
tpw1
td7
td8
td9
tr
tz
CPU Writes to Internal Register
DESCRIPTION
MIN
READYD low delay (CPU Handshake)
-
IOEN high delay (CPU Handshake)
-
READYD pulse width (CPU Handshake)
50
Internal Register delay (write)
-
Register Data/Address set-up time
-
Register Data/Address hold time
-
READYD to STRBD release
-
(SELECT • STRBD) to IOEN
-
MAX
150
20
-
60
30
0
1.37
1.8
UNITS
ns
ns
ns
ns
ns
ns
µs
µs
Figure 28 – CPU Writes to Internal Register
Aeroflex Circuit Technology
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SCDCT2553 REV B 8/6/99 Plainview NY [phone]