CT2553 Datasheet, PDF (30/36 Pages) Aeroflex Circuit Technology – CT2553 / 2554 / 2555 / 2556 Advanced Integrated MUX (AIM) Hybrid FOR MIL-STD-1553

16MHz Clock
(Internal)
STRBD
SELECT
IOEN
READYD
MEM/REG
RD/WR
A02
See Note 1
tz
td1
See Note 2
td6
tr
td2
tpw1
A01
A00
SSFLAG, SSBUSY, SVCRQST
DBAC, RTU/BC, MT, CTLIN B/A
D15-D00
DATA VALID
NOTE:
1. STRBD to IOEN (low) delay is two clock cycles. If contention occurs, delay is two clock cycles following release of bus.
2. CPU must release STRBD within 1.5µs of IOEN going active. READYD will go away within one clock cycle maximum.
SYMBOL
td1
td2
tpw1
td6
tr
tz
CPU Reads from Internal Register
DESCRIPTION
MIN
READYD low delay (CPU Handshake)
-
IOEN high delay (CPU Handshake)
-
READYD pulse width (CPU Handshake)
70
Internal Register delay (read)
-
READYD to STRBD release
-
(SELECT • STRBD) to IOEN
-
MAX
200
20
-
60
1.37
1.8
UNITS
ns
ns
ns
ns
µs
µs
Figure 33 – CPU Reads from Internal Register Timing
Aeroflex Circuit Technology
30
SCDCT2553 REV B 8/6/99 Plainview NY [phone]