CT2553 Datasheet, PDF (26/36 Pages) Aeroflex Circuit Technology – CT2553 / 2554 / 2555 / 2556 Advanced Integrated MUX (AIM) Hybrid FOR MIL-STD-1553

16MHz Clock
(Internal)
STRBD)
SELECT
IOEN
READYD
MEM/REG
See Note 1
tz
td8
td1
See Note 2
tr
tpw1
td2
td9
RD/WR
A02
A01
A00
EXTLD
D15-D00
VALID
VALID
td5
tpw6
CPU DATA
NOTE:
1. STRBD to IOEN (low) delay is two clock cycles. If contention occurs, delay is two clock cycles following release of bus.
2. CPU must release STRBD within 1.5µs of IOEN going active. READYD will go away within one clock cycle maximum.
SYMBOL
td1
td2
tpw1
td5
td8
td9
tpw6
tr
tz
CPU Writes to External Register
DESCRIPTION
MIN
READYD low delay (CPU Handshake)
-
IOEN high delay (CPU Handshake)
-
READYD pulse width (CPU Handshake)
50
EXTLD low delay
50
Register Data/Address set-up time
-
Register Data/Address set-up time
-
EXTLD low pulse width
56
READYD to STRBD release
-
(SELECT • STRBD) to IOEN
-
MAX
150
20
-
-
30
0
-
1.37
1.8
UNITS
ns
ns
ns
ns
ns
ns
ns
µs
µs
Figure 29 – CPU Writes to External Register
Aeroflex Circuit Technology
26
SCDCT2553 REV B 8/6/99 Plainview NY [phone]