CT2553 Datasheet, PDF (27/36 Pages) Aeroflex Circuit Technology – CT2553 / 2554 / 2555 / 2556 Advanced Integrated MUX (AIM) Hybrid FOR MIL-STD-1553

16MHz Clock
(Internal)
STRBD
SELECT
IOEN
READYD
MEM/REG
RD/WR
MEMCS
(Internal)
MEMOE
A15-A00
D15-D00
tr
See Note 1
tz
See Note 2
td1
td2
tpw1
td4
RAM ADDRESS VALID
RAM DATA VALID
NOTE:
1. STRBD to IOEN (low) delay is two clock cycles. If contention occurs, delay is two clock cycles following release of bus.
2. CPU must release STRBD within 1.5µs of IOEN going active. READYD will go away within one clock cycle maximum.
CPU Reads from RAM
SYMBOL
DESCRIPTION
MIN
td1
READYD low delay (CPU Handshake)
-
td2
IOEN high delay (CPU Handshake)
-
tpw1
READYD pulse width (CPU Handshake)
50
td4
CPU MEMOE low delay
-
tr
READYD to STRBD release
-
tz
(SELECT • STRBD) to IOEN
-
MAX
150
20
-
100
1.37
1.8
UNITS
ns
ns
ns
ns
µs
µs
Aeroflex Circuit Technology
Figure 30 – CPU Reads from RAM Timing
27
SCDCT2553 REV B 8/6/99 Plainview NY [phone]