CT2553 Datasheet, PDF (29/36 Pages) Aeroflex Circuit Technology – CT2553 / 2554 / 2555 / 2556 Advanced Integrated MUX (AIM) Hybrid FOR MIL-STD-1553

16MHz Clock
(Internal)
STRBD
SELECT
IOEN
READYD
MEM/REG
See Note
td1
tz
td8
tr
td2
tpw1
RD/WR
A02 (38)
A01
A00
EXTEN
D15-D00
DATA FROM EXTERNAL REGISTER
NOTE: STRBD to IOEN (low) delay is two clock cycles. If contention occurs, delay is two clock cycles following release of bus.
SYMBOL
td1
td2
tpw1
td8
tr
tz
CPU Reads from External Register Timing
DESCRIPTION
MIN
READYD low delay (CPU Handshake)
-
IOEN high delay (CPU Handshake)
-
READYD pulse width (CPU Handshake)
50
Register Data/Address set-up time
-
READYD to STRBD release
-
(SELECT • STRBD) to IOEN
-
MAX
150
20
-
40
1.37
1.8
UNITS
ns
ns
ns
ns
µs
µs
Aeroflex Circuit Technology
Figure 32 – CPU Reads from External Register Timing
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SCDCT2553 REV B 8/6/99 Plainview NY [phone]