COREMP7 Datasheet, PDF (8/30 Pages) Actel Corporation – CoreMP7

CoreMP7
Link Register
Register 14 is used as the subroutine Link Register
(LR).
Register 14 (r14) receives a copy of r15 when a Branch
with Link (BL) instruction is executed.
At all other times, you can treat r14 as a general-
purpose register.
The corresponding banked registers—r14_svc,
r14_irq, r14_fiq, r14_abt, and r14_und—are similarly
used to hold the return values of r15 when interrupts
and exceptions arise, or when BL instructions are
executed within interrupt or exception routines.
Program Counter
Register 15 holds the Program Counter (PC).
In ARM state, bits [1:0] of r15 are zero. Bits [31:2]
contain the PC.
In Thumb state, bit [0] is zero. Bits [31:1] contain the PC.
In privileged modes, another register, the Saved Program
Status Register (SPSR), is accessible. This contains the
condition code flags, and the mode bits saved as a result
of the exception that caused entry to the current mode.
Figure 4 shows the ARM state registers.
ARM State General Registers and Program Counter
System and User
r0
r1
r2
r3
r4
r5
r6
r7
r8
r9
r10
r11
r12
r13
r14
r15 (PC)
FIQ
r0
r1
r2
r3
r4
r5
r6
r7
r8_fiq
r9_fiq
r10_fiq
r11_fiq
r12_fiq
r13_fiq
r14_fiq
r15 (PC)
Supervisor
r0
r1
r2
r3
r4
r5
r6
r7
r8
r9
r10
r11
r12
r13_svc
r14_svc
r15 (PC)
Abort
r0
r1
r2
r3
r4
r5
r6
r7
r8
r9
r10
r11
r12
r13_abt
r14_abt
r15 (PC)
IRQ
r0
r1
r2
r3
r4
r5
r6
r7
r8
r9
r10
r11
r12
r13_irq
r14_irq
r15 (PC)
CPSR
ARM State Program Status Registers
CPSR
SPSR_fiq
CPSR
SPSR_svc
CPSR
SPSR_abt
CPSR
SPSR_irq
Undefined
r0
r1
r2
r3
r4
r5
r6
r7
r8
r9
r10
r11
r12
r13_und
r14_und
r15 (PC)
CPSR
SPSR_und
Figure 4 •
= banked register
CoreMP7 Register Organization in the ARM State
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v2.6