COREMP7 Datasheet, PDF (23/30 Pages) Actel Corporation – CoreMP7

Table 6 • AC Timing Parameters (Continued)
Symbol
Parameter
t_IHEXC
nFIQ, nIRQ, nRESET hold from rising CLK
t_ISCFG
CFGBIGEND setup to rising CLK
t_IHCFG
CFGBIGEND hold from rising CLK
t_ISDBGCTL
DBGBREAK, DBGEXT, DBGRQ input setup to rising CLK
t_ISDBGSTAT
Debug status inputs setup to rising CLK
t_IHDBGSTAT
Debug status inputs hold from rising CLK
t_OVDBGCTL
Rising CLK to debug control valid
t_OHDBCTL
Debug control hold time from rising CLK
t_ISTCLKEN
DBGTCKEN input setup to rising CLK
t_IHTCKEN
DBGTCKEN input hold from rising CLK
t_ISTCTL
DBGTDI, DBGTMS input setup to rising CLK
t_IHTCTL
DBGTDI, DBGTMS input hold from rising CLK
t_OVTDO
Rising CLK to DBGTDO valid
t_OHTDO
DBGTDO hold time from rising CLK
t_OVDBGSTAT
Rising CLK to debug status valid
t_OHDBGSTAT
Debug status hold time
Notes:
1. t_IHCLKEN is 0 ns for the Core Plus Debug variant in all devices.
2. t_IHCLKEN is 1 ns for the Core Only variant in all devices.
3. t_IHRDATA is 0 ns for Core Plus Debug variant in all devices.
4. t_IHRDATA is 1 ns for Core Only variant in all devices.
Min
–
10%
–
10%
10%
–
–
>0%
60%‘
–
35%
–
–
>0%
40%
>0%
CoreMP7
Max
0%
–
0%
–
–
0%
40%
–
–
0%
–
0%
20%
–
–
–
Debug
The ARM Debug Architecture uses a protocol converter
box to allow the debugger to talk via a Joint Test Action
Group (JTAG) port directly to the core. In effect, the scan
chains in the core that are required for test are re-used
for debugging.
The architecture uses the scan chains to insert
instructions directly in to the ARM core. The instructions
are executed on the core and, depending on the type of
instruction that has been inserted, the core or the system
state can be examined, saved, or changed. The
architecture has the ability to execute instructions at a
slow debug speed or to execute instructions at system
speed (for example, if access to an external memory was
required).
The fact that the debugger is actually using the JTAG
scan chains to access the core is of no importance to the
user, as the front end debugger remains exactly the
same. The user could still use the debugger with a
monitor program running on the target system or with
an instruction set simulator that runs on the debugger
host. In each case the debugging environment is the
same.
The advantages of using the JTAG port are:
• Hardware access required by a system for test is re-
used for debug.
• Core state and system state can be examined via
the JTAG port.
• The target system does not have to be running in
order to start debug.
A monitor program for example requires that some
target resources are running in order for the monitor
program to run.
• Traditional breakpoints and watchpoints are
available.
• On-chip resources can be supplemented.
• For example, the ARM Debug Architecture uses an
on-chip macro-cell to enhance the debugging
facilities available.
v2.6
23