COREMP7 Datasheet, PDF (6/30 Pages) Actel Corporation – CoreMP7

CoreMP7
Table 2 • Signal Descriptions (Continued)
Name
Type
Description
DBGnTRST
Input
Test reset
DBGRQ
Input
Debug request
DBGTCKEN
Input
Test clock enable
DBGTDI
Input
EICE data in
DBGTMS
Input
EICE mode select
nFIQ
Input
Interrupt request
nIRQ
Input
Fast interrupt request
nRESET
Input
Reset
RDATA[31:0]
Input
Read data bus
ADDR[31:0]
Output
Address bus
CPnI
Output
Coprocessor instruction (asserted low)
CPnMREQ
Output
Memory request (asserted low)
CPnOPC
Output
Opcode fetch (asserted low)
CPnTRANS
Output
Memory translate (asserted low)
CPSEQ
Output
Sequential address
CPTBIT
Output
Processor in Thumb mode
DBGACK
Output
Debug acknowledge
DBGCOMMRX
Output
EICE communication channel receive
DBGCOMMTX
Output
EICE communication channel transmit
DBGnEXEC
Output
Executed (asserted low)
DBGnTDOEN
Output
TDO enable (asserted low)
DBGRNG[1:0]
Output
EICE rangeout
DBGTDO
Output
EICE data out
DBGINSTRVALID
Output
ETM Instruction valid indicator
DMORE
Output
Set when next data memory access is followed by a sequential data
memory access
LOCK
Output
Locked transaction operation
PROT[1:0]
Output
Indicates code, data, or privilege level
SIZE[1:0]
Output
Memory access width
TRANS
Output
Next transaction type (i, n, s)
WDATA[31:0]
Output
Write data bus
WRITE
Output
Indicates write access
Note: The CoreMP7 is available with either the native ARM7 bus interface or with an AHB wrapper. The use of the AHB wrapper changes
or transforms some of the signals in Table 2. This is discussed in detail later in this document.
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