COREMP7 Datasheet, PDF (14/30 Pages) Actel Corporation – CoreMP7

CoreMP7
Delivery and Deployment
The CoreMP7 is delivered in CoreConsole, and can be
instantiated in design projects created in Libero IDE. The
files included with CoreMP7 consist of the Bus Functional
Model (BFM) files and test wrapper, AHB wrapper, and
the A7S secured CDB file. The A7S secured CDB file is
instantiated on the user device at programming. This
deployment flow is implemented to ensure that the
design is kept completely secure at all times, and allows
CoreMP7 to be easily used with the standard design flow
through the Libero IDE tool suite.
Bus Functional Model
During the development of an FPGA-based SoC, a
number of stages of testing may be undertaken. This can
involve some, or all, of the following approaches:
• Hardware simulation, using Verilog or VHDL
• Software simulation, using a host-based
instruction set simulator (ISS) of the SoC's
processor
• Hardware and software co-verification, using a
fully functional model of the processor in Verilog,
VHDL, or SWIFT form, or using a tool such as
Seamless
Due to the rapid prototyping capability of FPGAs,
however, integration of hardware and software often
occurs earlier in the SoC development cycle for FPGA
targets than it would for ASIC targets. Therefore,
hardware and software co-verification, which can be
very slow, is not a critical issue except in the most
complex FPGA-based SoCs.
The planned availability of ARM-based SoC solutions to
Actel FPGA customers necessitates that Actel provide
support for the test approaches described above. In
particular, there should be an emphasis on providing
solutions for hardware simulation and for software
simulation.
A software simulation solution is already available to
customers as part of the proposed ARM package. This
package contains the RealView Instruction Set Simulator,
which provides ARM7 instruction accurate simulation, as
well as powerful features, such as integration with the
RealView debugger.
Support for hardware simulation is also proposed. The
CoreConsole SoC configuration utility provides a means
for the developer to stitch together IP blocks using a bus
fabric of choice. It generates a system testbench,
controlled by a script-driven, bus functional model (BFM)
of the ARM7 processor. The ARM7 BFM allows the
developer to model low-level bus transactions, which
allow verification of connectivity of the various IP blocks
and the system memory map presented to the ARM7 by
the rest of the hardware.
This document specifies the following aspects of the
ARM7 BFM:
• Functionality
• BFM usage flow
• BFM script language
• Platforms
• Supported simulation tools
• Example BFM use case
BFM Usage Flow
As the BFM is part of an overall system test strategy, it is
helpful to look at the context in which it is used. Figure 9
on page 15 shows the various components within an
example system-level testbench that can be generated by
CoreConsole.
In Figure 9 on page 15, it is assumed that the developer
specifies an SoC subsystem by selecting the processor, bus
fabric, IP blocks, and memory subsystem in CoreConsole.
In this example, the user selects the following:
• ARM7 processor,
• AMBA AHB bus fabric
• MAC 10/100 IP core
• CoreUART IP core
• External SSRAM and Flash memory
As a result of constructing the CoreConsole subsystem,
the memory map for the system is created. Based on this
information, CoreConsole generates the following
outputs, among others:
• Verilog/VHDL model of SoC subsystem
• Verilog/VHDL models of IP cores
• Verilog/VHDL model of ARM7 BFM
• BFM test script
• System-level skeleton testbench
The BFM acts as a pin-for-pin replacement of the
ARM7TDMI-S in the SoC subsystem. It initiates bus
transactions on the native ARM7 bus, which are cycle-
accurate with real bus cycles that the ARM7TDMI-S
would produce. It has no knowledge, however, of real
ARM7 instructions.
At this point, the BFM may be used to run a basic test of
the SoC subsystem using the skeleton system testbench.
The BFM is fully integrated into the CoreConsole user
flow. In particular, if the user has an AHB-based CoreMP7
subsystem, CoreConsole automatically derives the
memory map of the user's subsystem. CoreConsole uses
this information to generate an overall BFM test script,
which includes customized "scriptlets" for each resource
attached to the AHB or APB buses.
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