COREMP7 Datasheet, PDF (22/30 Pages) Actel Corporation – CoreMP7

CoreMP7
AC Timing Parameter Definitions
Table 6 shows target AC parameters. All figures are expressed as percentages of the CLK period at maximum
operating frequency.
Note: Where 0% is shown, this indicates the hold time to clock edge plus the maximum clock skew for internal clock
buffering.
Table 6 •
Symbol
AC Timing Parameters
Parameter
Min
Max
t_CYC
CLK cycle time
t_ISCLKEN
CLKEN input setup to rising CLK
t_IHCLKEN
CLKEN input hold from rising CLK
t_ISABORT
ABORT input setup to rising CLK
t_IHABORT
ABORT input hold from rising CLK
t_ISRDATA
RDATA input setup to rising CLK
t_ISRST
nRESET input setup to rising CLK
t_ISTRST
DBGnTRST input setup to rising CLK
t_IHRDATA
RDATA input hold from rising CLK
t_OCPTBIT
Rising CLK to CPTBIT valid
t_ODBG
Rising CLK to DBGnEXEC, DBGINSTRVALID valid
t_OLOMO
Rising CLK to DMORE, LOCK valid
t_OVADDR
Rising CLK to ADDR valid
t_OHADDR
ADDR hold time from rising CLK
t_OVCTL
Rising CLK to control valid
t_OHCTL
Control hold time from rising CLK
t_OVTRANS
Rising CLK to transaction type valid
t_OHTRANS
Transaction type hold time from rising CLK
t_OVWDATA
Rising CLK to WDATA valid
t_OHWDATA
WDATA hold time from rising CLK
t_ISCPSTAT
CPA, CPB input setup to rising CLK
t_IHCPSTAT
CPA, CPB input hold from rising CLK
t_OVCPCTL
Rising CLK to coprocessor control valid
t_OHCPCTL
Coprocessor control hold time from rising CLK
t_OVCPNI
Rising CLK to coprocessor CPnI valid
t_OHCPNI
Coprocessor CPnI hold time from rising CLK
t_ISEXC
nFIQ, nIRQ, input setup to rising CLK
Notes:
1. t_IHCLKEN is 0 ns for the Core Plus Debug variant in all devices.
2. t_IHCLKEN is 1 ns for the Core Only variant in all devices.
3. t_IHRDATA is 0 ns for Core Plus Debug variant in all devices.
4. t_IHRDATA is 1 ns for Core Only variant in all devices.
100%
60%
–
40%
–
10%
90%
25%
–
–
–
–
–
>0%
–
>0%
–
>0%
–
>0%
20%
–
–
>0%
–
>0%
10%
–
–
See notes ^{1, 2}
–
0%
–
–
See notes ^{3, 4}
90%
40%
90%
90%
–
90%
–
50%
–
40%
–
–
0%
80%
–
40%
–
–
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