COREMP7 Datasheet, PDF (12/30 Pages) Actel Corporation – CoreMP7

CoreMP7
AHB Wrapper
The AHB wrapper interfaces between the CoreMP7 native ARM7 interface and the AHB bus. The module translates
access from the core to AHB accesses when the core is the current master. The external interface signals from the
wrapper are described in Table 3.
Table 3 • AHB Wrapper External Interface
Signal
External Master I/F
Direction
Description
HCLK
Input
Bus clock. This clock times all bus transfers. All signal timings are related to the rising
edge of HCLK.
HRESETn
Input
Reset. The bus reset signal is active LOW and is used to reset the system and the bus.
This is the only active LOW AHB signal.
HREADY
Input
Transfer done. When HIGH the HREADY signal indicates that a transfer has finished on
the bus. This signal can be driven LOW to extend a transfer.
HRESP[1:0]
Input Transfer response. Indicates an OKAY, ERROR, RETRY, or SPLIT response.
HGRANT
Input
Bus grant. Indicates that the CoreMP7 is currently the highest priority master.
Ownership of the address/control signals changes at the end of a transfer when
HREADY is HIGH, so a master gains access to the bus when both HREADY and
HGRANT are HIGH.
HADDR[31:0]
Output This is the 32-bit system address bus.
HTRANS[1:0]
Output Transfer type. Indicates the type of the current transfer.
HWRITE
Output
Transfer direction. When HIGH this signal indicates a write transfer and when LOW a
read transfer.
HSIZE[2:0]
Output
Transfer size. Indicates the size of the transfer, which can be byte (8-bit), halfword (16-
bit), or word (32-bit).
HBURST[2:0]
Output
Burst type. Indicates if the transfer forms part of a burst. The CoreMP7 performs
incrementing bursts of type INCR.
HPROT[3:0]
Output
Protection control. These signals indicate if the transfer is an opcode fetch or data
access, and if the transfer is a Supervisor mode access or User mode access.
HWDATA[31:0]
Output 32-bit data from the MASTER.
HRDATA[31:0]
Input 32-bit data written back to the MASTER.
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