COREMP7 Datasheet, PDF (11/30 Pages) Actel Corporation – CoreMP7

CoreMP7
The Program Status Registers
The CoreMP7 core contains a CPSR and five SPSRs for exception handlers to use. The program status registers the
following:
• Hold the condition code flags
• Control the enabling and disabling of interrupts
• Set the processor operating mode
The arrangement of bits is shown in Figure 7.
Condition
Code Flags
Reserved
Control Bits
31 30 29 28 27 26 25 24 23
NZCV
876543210
I F T M4 M3 M2 M1 M0
Overflow
Carry or Borrow or Extend
Zero
Negative or Less Than
Mode Bits
State Bit
FIQ Disable
IRQ Disable
Figure 7 • Program Status Register Format
The Condition Code Flags
The N, Z, C, and V bits are the condition code flags. You can set these bits by arithmetic and logical operations. The
flags can also be set by MSR and LDM instructions. The CoreMP7 processor tests these flags to determine whether to
execute an instruction.
All instructions can be executed conditionally in ARM state. In Thumb state, only the Branch instruction can be
executed conditionally. For more information about conditional execution, see the ARM Architecture Reference
Manual.
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