U1AFS250-FG256 Datasheet, PDF (5/27 Pages) Actel Corporation – 3 - DC and Power Characteristics

Actel Fusion Mixed-Signal FPGA for the MicroBlade AdvancedMC Solution
Table 3-5 • FPGA Programming, Storage, and Operating Limits
Product
Grade
Commercial
Element
FPGA/FlashROM
Embedded Flash
Grade Programming
Cycles
500
1k
15 k
Retention
20 years²
20 years²
5 years²
Storage Temperature (°C)
Minimum
Maximum
0
85
0
85
0
85
Industrial
FPGA/FlashROM
500
20 years
–40
85
Embedded Flash
1k
20 years
–40
85
15 k
5 years
–40
85
Notes:
1. This is a stress rating only. Functional operation at any condition other than those indicated is not implied.
2. If the embedded flash has been programmed less than 1 k times, every time it is programmed, the data will
hold for 20 years. If the embedded flash has been programmed more than 1 k times but less than 15 k
times, every time it is programmed, the data will hold for 5 years.
I/O Power-Up and Supply Voltage Thresholds for Power-On Reset
(Commercial and Industrial)
Sophisticated power-up management circuitry is designed into every Fusion device. These circuits
ensure easy transition from the powered off state to the powered up state of the device. The many
different supplies can power up in any sequence with minimized current spikes or surges. In
addition, the I/O will be in a known state through the power-up sequence. The basic principle is
shown in Figure 3-1 on page 3-6.
There are five regions to consider during power-up.
Fusion I/Os are activated only if ALL of the following three conditions are met:
1. V_CC and V_CCI are above the minimum specified trip points (Figure 3-1).
2. V_CCI > V_CC – 0.75 V (typical).
3. Chip is in the operating mode.
V_CCI Trip Point:
Ramping up: 0.6 V < trip_point_up < 1.2 V
Ramping down: 0.5 V < trip_point_down < 1.1 V
V_CC Trip Point:
Ramping up: 0.6 V < trip_point_up < 1.1 V
Ramping down: 0.5 V < trip_point_down < 1 V
V_CC and V_CCI ramp-up trip points are about 100 mV higher than ramp-down trip points. This
specifically built-in hysteresis prevents undesirable power-up oscillations and current surges. Note
the following:
• During programming, I/Os become tristated and weakly pulled up to V_CCI.
• JTAG supply, PLL power supplies, and charge pump V_PUMP supply have no influence on I/O
behavior.
Internal Power-Up Activation Sequence
1. Core
2. Input buffers
3. Output buffers, after 200 ns delay from input buffer activation
Preliminary v0.4
3-5