U1AFS250-FG256 Datasheet, PDF (22/27 Pages) Actel Corporation – 3 - DC and Power Characteristics

DC and Power Characteristics
Example of Power Calculation
This example considers a shift register with 5,000 storage tiles, including a counter and memory
that stores analog information. The shift register is clocked at 50 MHz and stores and reads
information from a RAM.
The device used is a commercial U1AFS600 device operating in typical conditions.
The calculation below uses the power calculation methodology previously presented and shows
how to determine the dynamic and static power consumption of resources used in the application.
Also included in the example is the calculation of power consumption in operating, standby, and
sleep modes to illustrate the benefit of power-saving modes.
Global Clock Contribution—P_CLOCK
F_CLK = 50 MHz
Number of sequential VersaTiles: N_S-CELL = 5,000
Estimated number of Spines: N_SPINES = 5
Estimated number of Rows: N_ROW = 313
Operating Mode
P_CLOCK = (P_AC1 + N_SPINE * P_AC2 + N_ROW * PAC3 + N_S-CELL * P_AC4) * F_CLK
P_CLOCK = (0.0128 + 5 * 0.0019 + 313 * 0.00081 + 5,000 * 0.00011) * 50
P_CLOCK = 41.28 mW
Standby Mode and Sleep Mode
P_CLOCK = 0 W
Logic—Sequential Cells, Combinational Cells, and Routing Net Contributions—P_S-CELL,
P_C-CELL, and P_NET
F_CLK = 50 MHz
Number of sequential VersaTiles: N_S-CELL = 5,000
Number of combinatorial VersaTiles: N_C-CELL = 6,000
Estimated toggle rate of VersaTile outputs: α₁ = 0.1 (10%)
Operating Mode
P_S-CELL = N_S-CELL * (P_AC5+ (α₁ / 2) * P_AC6) * F_CLK
P_S-CELL = 5,000 * (0.00007 + (0.1 / 2) * 0.00029) * 50
P_S-CELL = 21.13 mW
P_C-CELL = N_C-CELL* (α₁ / 2) * P_AC7 * F_CLK
P_C-CELL = 6,000 * (0.1 / 2) * 0.00029 * 50
P_C-CELL = 4.35 mW
P_NET = (N_S-CELL + N_C-CELL) * (α₁ / 2) * P_AC8 * F_CLK
P_NET = (5,000 + 6,000) * (0.1 / 2) * 0.0007 * 50
P_NET = 19.25 mW
P_LOGIC = P_S-CELL + P_C-CELL + P_NET
P_LOGIC = 21.13 mW + 4.35 mW + 19.25 mW
P_LOGIC = 44.73 mW
Standby Mode and Sleep Mode
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Preliminary v0.4