U1AFS250-FG256 Datasheet, PDF (13/27 Pages) Actel Corporation – 3 - DC and Power Characteristics

Actel Fusion Mixed-Signal FPGA for the MicroBlade AdvancedMC Solution
Table 3-10 • Summary of I/O Output Buffer Power (per pin)—Default I/O Software Settings¹
Applicable to Pro I/O Banks
C_LOAD (pF)
V_CCI (V)
Static Power
P_DC8 (mW)²
Dynamic Power
P_AC10 (µW/MHz)³
Single-Ended
3.3 V LVTTL/LVCMOS
35
3.3
–
474.70
2.5 V LVCMOS
35
2.5
–
270.73
1.8 V LVCMOS
35
1.8
–
151.78
1.5 V LVCMOS (JESD8-11)
35
1.5
–
104.55
3.3 V PCI
10
3.3
–
204.61
3.3 V PCI-X
10
3.3
–
204.61
Voltage-Referenced
3.3 V GTL
10
3.3
–
24.08
2.5 V GTL
10
2.5
–
13.52
3.3 V GTL+
10
3.3
–
24.10
2.5 V GTL+
10
2.5
–
13.54
HSTL (I)
20
1.5
7.08
26.22
HSTL (II)
20
1.5
13.88
27.22
SSTL2 (I)
30
2.5
16.69
105.56
SSTL2 (II)
30
2.5
25.91
116.60
SSTL3 (I)
30
3.3
26.02
114.87
SSTL3 (II)
30
3.3
42.21
131.76
Differential
LVDS
–
2.5
7.70
89.62
LVPECL
–
3.3
19.42
168.02
Applicable to Advanced I/O Banks
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS
35
3.3
–
468.67
2.5 V LVCMOS
35
2.5
–
267.48
1.8 V LVCMOS
35
1.8
–
149.46
1.5 V LVCMOS (JESD8-11)
35
1.5
–
103.12
3.3 V PCI
10
3.3
–
201.02
3.3 V PCI-X
10
3.3
–
201.02
Notes:
1. Dynamic power consumption is given for standard load and software-default drive strength and output
slew.
2. P_DC8 is the static power (where applicable) measured on V_CCI.
3. P_AC10 is the total dynamic power measured on V_CC and V_CCI.
Preliminary v0.4
3 - 13