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U1AFS250-FG256 Datasheet, PDF (17/27 Pages) Actel Corporation – 3 - DC and Power Characteristics
Actel Fusion Mixed-Signal FPGA for the MicroBlade AdvancedMC Solution
Power Calculation Methodology
This section describes a simplified method to estimate power consumption of an application. For
more accurate and detailed power estimations, use the SmartPower tool in the Libero IDE
software.
The power calculation methodology described below uses the following variables:
• The number of PLLs as well as the number and the frequency of each output clock
generated
• The number of combinatorial and sequential cells used in the design
• The internal clock frequencies
• The number and the standard of I/O pins used in the design
• The number of RAM blocks used in the design
• The number of NVM blocks used in the design
• The number of Analog Quads used in the design
• Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table 3-13 on
page 3-21.
• Enable rates of output buffers—guidelines are provided for typical applications in
Table 3-14 on page 3-21.
• Read rate and write rate to the RAM—guidelines are provided for typical applications in
Table 3-14 on page 3-21.
• Read rate to the NVM blocks
The calculation should be repeated for each clock domain defined in the design.
Methodology
Total Power Consumption—PTOTAL
Operating Mode, Standby Mode, and Sleep Mode
PTOTAL = PSTAT + PDYN
PSTAT is the total static power consumption.
PDYN is the total dynamic power consumption.
Total Static Power Consumption—PSTAT
Operating Mode
PSTAT = PDC1 + (NNVM-BLOCKS * PDC4) + PDC5+ (NQUADS * PDC6) + (NINPUTS * PDC7) + (NOUTPUTS * PDC8) +
(NPLLS * PDC9)
NNVM-BLOCKS is the number of NVM blocks available in the device.
NQUADS is the number of Analog Quads used in the design.
NINPUTS is the number of I/O input buffers used in the design.
NOUTPUTS is the number of I/O output buffers used in the design.
NPLLS is the number of PLLs available in the device.
Standby Mode
PSTAT = PDC2
Sleep Mode
PSTAT = PDC3
Total Dynamic Power Consumption—PDYN
Operating Mode
PDYN = PCLOCK + PS-CELL + PC-CELL + PNET + PINPUTS + POUTPUTS + PMEMORY + PPLL + PNVM+ PXTL-OSC +
PRC-OSC + PAB
Preliminary v0.4
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