U1AFS250-FG256 Datasheet, PDF (21/27 Pages) Actel Corporation – 3 - DC and Power Characteristics

Actel Fusion Mixed-Signal FPGA for the MicroBlade AdvancedMC Solution
Guidelines
Toggle Rate Definition
A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage.
If the toggle rate of a net is 100%, this means that the net switches at half the clock frequency.
Below are some examples:
• The average toggle rate of a shift register is 100%, as all flip-flop outputs toggle at half of
the clock frequency.
• The average toggle rate of an 8-bit counter is 25%:
– Bit 0 (LSB) = 100%
– Bit 1 = 50%
– Bit 2 = 25%
–…
– Bit 7 (MSB) = 0.78125%
– Average toggle rate = (100% + 50% + 25% + 12.5% + . . . 0.78125%) / 8.
Enable Rate Definition
Output enable rate is the average percentage of time during which tristate outputs are enabled.
When non-tristate output buffers are used, the enable rate should be 100%.
Table 3-13 • Toggle Rate Guidelines Recommended for Power Calculation
Component
α₁
α₂
Definition
Toggle rate of VersaTile outputs
I/O buffer toggle rate
Guideline
10%
10%
Table 3-14 • Enable Rate Guidelines Recommended for Power Calculation
Component
β₁
β₂
β₃
β₄
Definition
I/O output buffer enable rate
RAM enable rate for read operations
RAM enable rate for write operations
NVM enable rate for read operations
Guideline
100%
12.5%
12.5%
0%
Preliminary v0.4
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