U1AFS250-FG256 Datasheet, PDF (19/27 Pages) Actel Corporation – 3 - DC and Power Characteristics

Actel Fusion Mixed-Signal FPGA for the MicroBlade AdvancedMC Solution
Standby Mode and Sleep Mode
P_NET = 0 W
I/O Input Buffer Dynamic Contribution—P_INPUTS
Operating Mode
P_INPUTS = N_INPUTS * (α₂ / 2) * P_AC9 * F_CLK
N_INPUTS is the number of I/O input buffers used in the design.
α₂ is the I/O buffer toggle rate—guidelines are provided in Table 3-13 on page 3-21.
F_CLK is the global clock signal frequency.
Standby Mode and Sleep Mode
P_INPUTS = 0 W
I/O Output Buffer Dynamic Contribution—P_OUTPUTS
Operating Mode
P_OUTPUTS = N_OUTPUTS * (α₂ / 2) * β₁ * P_AC10 * F_CLK
N_OUTPUTS is the number of I/O output buffers used in the design.
α₂ is the I/O buffer toggle rate—guidelines are provided in Table 3-13 on page 3-21.
β₁ is the I/O buffer enable rate—guidelines are provided in Table 3-14 on page 3-21.
F_CLK is the global clock signal frequency.
Standby Mode and Sleep Mode
P_OUTPUTS = 0 W
RAM Dynamic Contribution—P_MEMORY
Operating Mode
β β P_MEMORY = (N_BLOCKS * P_AC11 * ₂ * F_READ-CLOCK) + (N_BLOCKS * P_AC12 * ₃ * F_WRITE-CLOCK)
N_BLOCKS is the number of RAM blocks used in the design.
F_READ-CLOCK is the memory read clock frequency.
β₂ is the RAM enable rate for read operations—guidelines are provided in Table 3-14 on
page 3-21.
β₃ the RAM enable rate for write operations—guidelines are provided in Table 3-14 on
page 3-21.
F_WRITE-CLOCK is the memory write clock frequency.
Standby Mode and Sleep Mode
P_MEMORY = 0 W
PLL/CCC Dynamic Contribution—P_PLL
Operating Mode
P_PLL = P_AC13 * F_CLKOUT
F_CLKIN is the input clock frequency.
F_CLKOUT is the output clock frequency.¹
Standby Mode and Sleep Mode
P_PLL = 0 W
1. The PLL dynamic contribution depends on the input clock frequency, the number of output clock
signals generated by the PLL, and the frequency of each output clock. If a PLL is used to generate more
than one output clock, include each output clock in the formula output clock by adding its
corresponding contribution (P_AC14 * F_CLKOUT product) to the total PLL contribution.
Preliminary v0.4
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