EX128-TQG100A Datasheet, PDF (27/44 Pages) Actel Corporation – eX Automotive Family FPGAs

eX Automotive Family FPGAs
Table 1-17 • eX Family Timing Characteristics
(Worst-Case Automotive Conditions, V_CCA = 2.3 V, T_J = 125°C)
‘Std.’ Speed
Parameter
Description
Min.
Max.
Units
t_ENZL
Enable-to-Pad, Z to L
4.5
ns
t_ENZLS
Enable-to-Pad Z to L—Low Slew
21.2
ns
t_ENZH
Enable-to-Pad, Z to H
6.1
ns
t_ENLZ
Enable-to-Pad, L to Z
3.8
ns
t_ENHZ
Enable-to-Pad, H to Z
7.1
ns
d_TLH
Delta Delay vs. Load Low to High
0.058
ns/pF
d_THL
Delta Delay vs. Load High to Low
0.028
ns/pF
d_THLS
Delta Delay vs. Load High to Low—Low Slew
3.3 V LVTTL Output Module Timing¹ (V_CCI = 3.0 V)
0.090
ns/pF
t_DLH
Data-to-Pad Low to High
5.0
ns
t_DHL
Data-to-Pad High to Low
4.9
ns
t_DHLS
Data-to-Pad High to Low—Low Slew
17.4
ns
t_ENZL
Enable-to-Pad, Z to L
4.0
ns
t_ENZLS
Enable-to-Pad Z to L—Low Slew
17.4
ns
t_ENZH
Enable-to-Pad, Z to H
5.0
ns
t_ENLZ
Enable-to-Pad, L to Z
5.0
ns
t_ENHZ
Enable-to-Pad, H to Z
4.8
ns
d_TLH
Delta Delay vs. Load Low to High
0.038
ns/pF
d_THL
Delta Delay vs. Load High to Low
0.028
ns/pF
d_THLS
Delta Delay vs. Load High to Low—Low Slew
0.090
ns/pF
Notes:
1. For dual-module macros, use t_PD + t_RD1 + t_PDn, t_RCO + t_RD1 + t_PDn or t_PD1 + t_RD1 + t_SUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance.
3. Clock skew improves as the clock network becomes more heavily loaded.
4. Delays based on 35 pF loading.
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