EX128-TQG100A Datasheet, PDF (25/44 Pages) Actel Corporation – eX Automotive Family FPGAs

eX Automotive Family FPGAs
eX Family Timing Characteristics
Table 1-17 • eX Family Timing Characteristics
(Worst-Case Automotive Conditions, V_CCA = 2.3 V, T_J = 125°C)
‘Std.’ Speed
Parameter
Description
Min.
Max.
Units
C-Cell Propagation Delays¹
t_PD
Internal Array Module
Predicted Routing Delays²
1.1
ns
t_DC
t_FC
t_RD1
t_RD2
t_RD3
t_RD4
t_RD8
t_RD12
R-Cell Timing
FO=1 Routing Delay, DirectConnect
FO=1 Routing Delay, FastConnect
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
FO=12 Routing Delay
0.1
ns
0.6
ns
0.6
ns
0.7
ns
0.9
ns
1.1
ns
1.9
ns
2.8
ns
t_RCO
Sequential Clock-to-Q
t_CLR
Asynchronous Clear-to-Q
t_PRESET
Asynchronous Preset-to-Q
t_SUD
Flip-Flop Data Input Set-Up
t_HD
Flip-Flop Data Input Hold
t_WASYN
Asynchronous Pulse Width
t_RECASYN
Asynchronous Recovery Time
t_HASYN
Asynchronous Hold Time
2.5 V Input Module Propagation Delays
1.0
ns
0.9
ns
1.0
ns
0.8
ns
0.0
ns
2.2
ns
0.6
ns
0.6
ns
t_INYH
Input Data Pad-to-Y High
t_INYL
Input Data Pad-to-Y Low
3.3 V Input Module Propagation Delays
1.1
ns
1.4
ns
t_INYH
Input Data Pad-to-Y High
t_INYL
Input Data Pad-to-Y Low
Input Module Predicted Routing Delays²
1.3
ns
1.6
ns
t_IRD1
FO=1 Routing Delay
0.5
ns
t_IRD2
FO=2 Routing Delay
0.7
ns
t_IRD3
FO=3 Routing Delay
0.9
ns
Notes:
1. For dual-module macros, use t_PD + t_RD1 + t_PDn, t_RCO + t_RD1 + t_PDn or t_PD1 + t_RD1 + t_SUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance.
3. Clock skew improves as the clock network becomes more heavily loaded.
4. Delays based on 35 pF loading.
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