EX128-TQG100A Datasheet, PDF (21/44 Pages) Actel Corporation – eX Automotive Family FPGAs

eX Timing Model
eX Automotive Family FPGAs
Input Delays
I/O Module
t_INYH= 1.3 ns
t_IRD1 = 0.5 ns
t_IRD2 = 0.7 ns
Internal Delays
Combinatorial
Cell
Predicted
Routing
Delays
Output Delays
I/O Module
Routed
Clock
Hardwired
Clock
tt^SHUDD==00.0.8nnss
t_PD = 1.1 ns
Register
Cell
ttt_RRRDDD841
=
=
=
0.6
1.1
1.9
ns
ns
ns
t_DHL = 4.9 ns
I/O Module
DQ
t_RD1 = 0.6 ns
t_ENZL= 4.0 ns
t_DHL = 4.9 ns
t_RCKH= 2.3 ns
(100% Load)
t_RCO= 1.0 ns
I/O Module
t_INYH= 1.3 ns
t_IRD1 = 0.5 ns
t
t
SUD ^{= 0.8 ns}
HD ^{= 0.0 ns}
Register
Cell
DQ
t_RD1 = 0.6 ns
I/O Module
t_ENZL= 4.0 ns
t_DHL = 4.9 ns
t_HCKH= 1.8 ns
t_RCO= 1.0 ns
Note: *Values shown for eX128, worst-case automotive conditions (2.3 V V_CCA, 3.3 V V_CCI, 35 pF Pad Load).
Figure 1-15 • eX Timing Model
Hardwired Clock
External Setup = t_INYH + t_IRD1 + t_SUD – t_HCKH
= 1.3 + 0.5 + 0.8 – 1.8 = 0.8 ns
Clock-to-Out (Pad-to-Pad), typical
= t_HCKH + t_RCO + t_RD1 + t_DHL
= 1.8 + 1.0 + 0.6 + 4.9 = 8.3 ns
Routed Clock
External Setup = t_INYH + t_IRD2 + t_SUD – t_RCKH
= 1.3 + 0.7 + 0.8 – 2.3 = 0.5 ns
Clock-to-Out (Pad-to-Pad), typical
= t_RCKH + t_RCO + t_RD1 + t_DHL
= 2.3 + 1.0 + 0.6 + 4.9 = 8.8 ns
v3.2
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