EX128-TQG100A Datasheet, PDF (26/44 Pages) Actel Corporation – eX Automotive Family FPGAs

eX Automotive Family FPGAs
Table 1-17 • eX Family Timing Characteristics
(Worst-Case Automotive Conditions, V_CCA = 2.3 V, T_J = 125°C)
‘Std.’ Speed
Parameter
Description
Min.
Max.
Units
t_IRD4
FO=4 Routing Delay
t_IRD8
FO=8 Routing Delay
t_IRD12
FO=12 Routing Delay
Dedicated (Hardwired) Array Clock Networks
1.1
ns
1.9
ns
2.8
ns
t_HCKH
Input Low to High
(Pad to R-Cell Input)
1.8
ns
t_HCKL
Input High to Low
(Pad to R-Cell Input)
1.8
ns
t_HPWH
Minimum Pulse Width High
t_HPWL
Minimum Pulse Width Low
t_HCKSW
Maximum Skew
t_HP
Minimum Period
f_HMAX
Maximum Frequency
Routed Array Clock Networks
2.0
ns
2.0
ns
0.1
ns
4.0
ns
250
MHz
t_RCKH
Input Low to High (Light Load)
(Pad to R-Cell Input)
1.6
ns
t_RCKL
Input High to Low (Light Load)
(Pad to R-Cell Input)
1.6
ns
t_RCKH
Input Low to High (50% Load)
(Pad to R-Cell Input)
1.9
ns
t_RCKL
Input High to Low (50% Load)
(Pad to R-Cell Input)
1.9
ns
t_RCKH
Input Low to High (100% Load)
(Pad to R-Cell Input)
2.3
ns
t_RCKL
Input High to Low (100% Load)
(Pad to R-Cell Input)
2.3
ns
t_RPWH
Min. Pulse Width High
2.0
ns
t_RPWL
Min. Pulse Width Low
t_RCKSW3
Maximum Skew (Light Load)
t_RCKSW3
Maximum Skew (50% Load)
t_RCKSW3
Maximum Skew (100% Load)
2.5 V LVCMOS2 Output Module Timing⁴ (V_CCI = 2.3 V)
2.0
ns
0.3
ns
0.2
ns
0.1
ns
t_DLH
Data-to-Pad Low to High
5.9
ns
t_DHL
Data-to-Pad High to Low
6.3
ns
t_DHLS
Data-to-Pad High to Low—Low Slew
20.8
ns
Notes:
1. For dual-module macros, use t_PD + t_RD1 + t_PDn, t_RCO + t_RD1 + t_PDn or t_PD1 + t_RD1 + t_SUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance.
3. Clock skew improves as the clock network becomes more heavily loaded.
4. Delays based on 35 pF loading.
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