Z02215 Datasheet, PDF (69/74 Pages) Zilog, Inc. – Single Chip Modem with Integrated Controller, Data Pump, and Analog Front End

Z02215
Single Chip Modem with Integrated Controller, Data Pump, and AFE
63
CS
A0
RD
A
B
D(7..0) out
WR
D(7..0) in
Figure 12. Parallel Port Timing
C
D
F
E
Table 17. Serial Interface Timing
Description
RXD Data Valid Delay Time
TXD Data Setup Time
TXD Data Hold Time
Parameter Minimum
1
–
2
100
3
100
Typical Maximum
12
–
–
–
–
–
Units
ns
ns
ns
Table 18. Parallel Interface Timing
Description (Read Cycle)
CS, A0, or RD to Data valid
Data hold from CS, A0, or RD
CS, and A0 setup before WR
Data setup before WR
Data hold from WR
WR pulse width
Parameter
A
B
C
D
E
F
Minimum
0
15
5
5
10
Typical Maximum
25
Units
ns
ns
ns
ns
ns
ns
PS001907-0904
Capacitance