Z02215 Datasheet, PDF (17/74 Pages) Zilog, Inc. – Single Chip Modem with Integrated Controller, Data Pump, and Analog Front End

Z02215
Single Chip Modem with Integrated Controller, Data Pump, and AFE
11
7
RRIE
R/W
0
Bit No.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIDR is the data register for transmitting and receiving data, including the AT com-
mands.
In RECEIVE DATA mode (when HRD, HCS, HA0, S/P are Low), Z02215 reads
the data on the Host Parallel Data bus (HD0–HD7) for the external host to read
the contents.
In TRANSMIT DATA mode (when HWR, HCS, HA0, S/P are Low), Z02215 reads
the contents placed on the Host Parallel Data bus (HD0–HD7) by the external
host processor.
PISR is the Status register. Bits 0, 1, 6 and 7 of this register are defined in hard-
ware, and bits 2, 3, 4, and 5 are defined in software as follows:
Table 2. Status Register
6
TRIE
R/W
0
5
DCD
R/W
1
Mnemonic R/W
RRIE
R/W
TRIE
R/W
DCD
R/W
RBRK
R/W
DTR
R/W
SBRK
R/W
RRF
R/W
TRE
R/W
4
RBRK
R/W
0
Default
Value
0
0
1
0
0
0
0
1
3
DTR
R/W
0
2
SBRK
R/W
0
1
RRF
R/W
0
0
TRE
R/W
1
Description
Receive Register Interrupt Enable. When this bit is 1, the
Z02215 drives the HIRQ pin Low when RRF is 1.
Transmit Register Interrupt Enable. When this bit is 1, the
Z02215 drives the HIRQ pin Low when TRE is 1
DCD signal sent from the Z02215.
1–Active
0–Inactive
Break signal sent to the host. The Z02215 sets this bit to 1
to indicate that a line break is transmitted to the host. The
Z02215 resets this bit to 0 when the line break condition is
ended.
DTR signal sent to the Z02215.
1: Active
0: Inactive
Send Line Break to the Z02215. The host sets this bit to 1
to transmit a line break to the Z02215. The host sets this bit
to 0 to stop transmitting a line break. The host performs the
timing of the transmitted line break.
Receive Register Full. The host can receive a byte from the
Z02215 when this bit is 1.
Transmit Register Empty. The host can transmit a byte to
the Z02215 when this bit is 1.
PS001907-0904
Parallel Host Interface