Z02215 Datasheet, PDF (16/74 Pages) Zilog, Inc. – Single Chip Modem with Integrated Controller, Data Pump, and Analog Front End

Z02215
Single Chip Modem with Integrated Controller, Data Pump, and AFE
10
Table 1. Pin Descriptions (Continued)
PLCC LQFP
Symbol Pin # Pin # Function
Direction Description
Note: This comment applies to pins HD0–HD7, respectively.
HD0–HD7 are the Host Parallel Interface Data bus. Bi-directional, Active High, Parallel mode only. These pins
constitute an 8-bit bi-directional data bus used for the transfer of control and status information. HD0–HD7 are
3-stated except for a PIDT or PICR read.
DTR/HD0 36 19
Data Terminal Input
Ready
Serial mode only. This signal is asserted by
the DTE when it is ready to receive data.
RTS/HD1 37 20
Request To
Send
Input
Serial mode only. This signal indicates that the
DTE is ready to send data to the modem. When
the modem is ready, it asserts CTS (see CTS,
below).
PB2/HD2 38 21
General
Output
Purpose Output
Serial mode only. Programmable using
Diplomat™.
PB3/HD3 39 22
General
Output
Purpose Output
Serial mode only. Programmable using
Diplomat™.
DCD/HD4 40 23
Data Carrier
Detect
Output
Serial mode only. This signal indicates that a
modem carrier signal has been detected on the
line.
CTS/HD5 41 24
Clear To Send Output
Serial mode only. This signal indicates that the
modem is ready for the DTE to send data to it.
RI/HD6 42 25
Ring Indicator Output
Serial mode only. When active, this signal
indicates that a ring signal on the phone line is
detected by the modem.
DSR/HD7 43 26
Data Set Ready Output
Serial mode only. This pin is the Data Set
Ready pin and indicates when the modem is
ready to transmit data. Refer to the &S
command for details.
S/P
44 27
Serial or
Input
This pin configures the Z02215 Host interface to
Parallel Mode
Select
Serial or Parallel mode. When High (V_CC), the
Serial mode is selected and when this pin is tied
Low (GND), the Parallel mode is selected.
Parallel Host Interface
With the Parallel Host Interface, a host controller can put the Z02215 on its pro-
cessor bus and access it as a peripheral.The Parallel Interface consists of two
host registers:
• Register 0–Parallel Interface Data Register (PIDR)
• Register 1–Parallel Interface Status Register (PISR)
PS001907-0904
Parallel Host Interface