Z86U18 Datasheet, PDF (3/30 Pages) Zilog, Inc. – USB Device Controller with CMOS Z86K15 MCU

Zilog
Z86U18
USB Device Controller with CMOS Z86K15 MCU
USB FUNCTIONAL BLOCK DESCRIPTION
The USB portion of the chip is divided into two areas, the the host. Data flow into and out of the MCU portions is pro-
1 ^{transceiver and the Serial Interface Engine (SIE). The cessed through eight registers mapped into Expanded}
transceiver handles incoming differential signals and "sin- Register File Memory at locations 010 to 017.
gle ended zero" (SE0). It also converts output data in dig-
ital form to differential drive at the proper levels.
The USB SIE handles two endpoints (control at Endpoint
0 and data into the host from Endpoint 1). All communica-
The SIE does all other processing on incoming and out go- tions are at the 1.5 Mb/sec HID class data rate. Future de-
ing data. This includes signal recovery timing, bit stuffing, vices will handle the full 12 Mb/sec data rate.
validity checking, data sequencing, and handshaking to
Preamble
sent at full speed
Hub enables low
speed port outputs
SYNC PID Hub Setup SYNC
Token sent at low speed
PID
ENDP . . .
EOP
Hub enables low
speed port outputs
SYNC
Data packet sent at low speed
PID
DATA
CRC
EOP
Preamble
sent at full speed
Hub enables low
speed port outputs
Handshake sent at low speed
SYNC PID Hub Setup
SYNC
PID
EOP
Hub enables low
speed port outputs
Figure 2. Data To/From K86U18
USB SUSPEND/RESUME FUNCTIONALITY
Suspend is intitiated by the host only, when it stops send-
ing start of frame signaling or start of frame keep alive
pulse.
When SIE detects the absence of start of frame signaling
from the host for more than 3 miliseconds, it sets the Sus-
pend bit in Reg7 and the Supspend Interrupt bit in Reg6
which interrupts the microcontroller. There is also an inter-
nal Suspend node that reflects the state of the Suspend bit
in Reg7. This Suspend node is used to put the tranceiver
in Suspend mode. When the microcontroller gets the Sus-
pend Interrupt, it stops all the clocks.
Resume can be initiated by host or by UC. Host initiates
Resume by sending J to K transition on D+ and D- pins.
Upon detecting J to K transition, the GFI makes Resume-
out signal active, which is used to wake the UC. Once the
UC is up, it clears the suspend bit in Reg7. UC can initiate
Resume by writing 1 to Send Resume bit in Reg7 for long-
er than 10mSec. This makes GFI to send J to K transition
on D+ and D- pins which indicates to the host the Resume
state. After 10 msec UC also clears the Suspend bit in
Reg7.
U18 EMULATIONS AND CODE DEVELOPMENT
An existing ICEBOXª Emulator has been modified by the
addition of an adaptor board. This board includes a FPGA
with the logic of the SIE, a commercial USB transceiver,
and a voltage regulator. These three functions adapt our
Z86C15/K15 to the USB world allowing the customer to
develop code to be placed into the ROM of U18s.
The ICEBOX has complete functional equivalence to the
final part including pin out to the application board. This
begins with the 40-pin DIP and covers the other pin config-
urations. Once code has been verified, it can be released
to Zilog and placed into the ROM of the Z86U18.
DS97KEY0102
PRELIMINARY
3